ADFS5758 datasheet(32/75 Pages) AD

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ADFS5758

Data Sheet

Rev. 0 | Page 32 of 75

SERIAL INTERFACE

The ADFS5758 is controlled over a versatile 4-wire serial

interface that operates at clock rates of up to 50 MHz and is

compatible with SPI, QSPI, MICROWIRE, and DSP standards.

Data coding is always straight binary.

Input Shift Register

With SPI CRC enabled (default state), the input shift register is

32 bits wide. Data is loaded into the device MSB first as a 32-bit

word under the control of a serial clock input, SCLK. Data is

clocked in on the falling edge of SCLK. If CRC is disabled, the

serial interface is reduced to 24 bits. A 32-bit frame is still

accepted, but the last eight bits are ignored. See the Register

Map section for full details on the registers that can be

addressed via the SPI interface.

Table 7. Writing to a Register (CRC Enabled)

MSB

LSB

D31

D30:D29

D28:D24

D23:D8

D7:D0

Slip Bit

ADFS5758

address

Data

CRC

Transfer Function

Table 8 shows the input code to ideal output voltage relation-

ship for the ADFS5758 for straight binary data coding of the

±5 V output range.

Table 8. Ideal Output Voltage to Input Code Relationship

Digital Input, Straight Binary

Data Coding

Analog Output

MSB

LSB

VOUT

1111

+2 × VREF × (32,767/32,768)

1111

1110

+2 × VREF × (32,766/32,768)

1000

0000

0 V

0000

0001

−2 × VREF × (32,767/32,768)

0000

−2 × VREF

POWER-ON STATE OF THE ADFS5758

On initial power-on or a device reset, the voltage and current

output channel is disabled. The switch connecting VIOUT via a

30 kΩ pull-down resistor to AGND is open. This switch can be

configured in the DCDC_CONFIG2 register. VDPC+ is internally

driven to 4.8 V on power-on until the dc-to-dc converter is

enabled.

After device power-on, or a device reset, a calibration memory

refresh command is required (see the Echo Mode section). It is

recommended to wait 500 µs minimum after writing this

command, before writing further instructions to the device to

allow time for internal calibrations to take place (see Figure 93).

Power-On Reset

3.3V

VLDO

POWER-ON

RESET

SOFTWARE

RESET

HARDWARE

RESET

INT_AVDD

RESET

SDI

SCLK

VLDO

AVDD2

SYNC

Figure 76. Power-On Reset Block Diagram

The ADFS5758 incorporates a power-on reset circuit that

ensures the ADFS5758 is held in reset while the power supplies

are at a level insufficient to allow reliable operation. The power-

on reset circuit (see Figure 76) monitors the AVDD2 generated

VLDO and INT_AVCC voltages, the RESET pin, and the SPI

reset signal. The power-on reset circuit keeps the ADFS5758 in

reset until the voltages on the VLDO, and INT_AVCC nodes

are sufficient for reliable operation. If the power-on circuit

receives a signal from the RESET pin or if a software reset is

written to the ADFS5758 via the SPI interface, the ADFS5758 is

reset. Do not write SPI commands to the device within 100 μs

of a reset event.

POWER SUPPLY CONSIDERATIONS

The ADFS5758 has four supply rails: AVDD1, AVDD2, AVSS, and

VLOGIC. See the Specifications section for the voltage range of the

four supply rails and the associated conditions.

AVDD1 Considerations

AVDD1 is the supply rail for the dc-to-dc converter and can

range from 7 V to 33 V. Although the maximum value of AVDD1

is 33 V and the minimum value of AVSS is −33 V, the maximum

operating range of |AVDD1 to AVSS| is 60 V. VDPC+ is derived

from AVDD1, and its value depends on the mode of operation of

the dc-to-dc converter.

The dc-to-dc converter requires a sufficient level of margin to

be maintained between AVDD1 and VDPC+ to ensure the dc-to-dc

circuitry operates correctly. This margin is 5% of the maximum

VDPC+ voltage for a given mode of operation.

Table 9. AVDD1 to VDPC+ Margin

Mode of Operation

VDPC+ Maximum

DPC Voltage Mode

15 V

DPC Current Mode

(IOUT maximum × RLOAD) + IOUT headroom

PPC Current Mode

DCDC_CONFIG1, Bits[4:0] programmed

value

See the Power Dissipation Control section for further details on

the dc-to-dc converter modes of operation.

ADFS5758 Datasheet(PDF) 32 Page - Analog Devices

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