ADFS5758 datasheet(14/75 Pages) AD

14 / 75 page

ADFS5758

Data Sheet

Rev. 0 | Page 14 of 75

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to

±200 mA do not cause silicon controlled rectifier (SCR) latch-up.

Table 4.

Parameter

Rating

AVDD1 to AGND, DGND

−0.3 V to +44 V

AVSS to AGND, DGND

+0.3 V to −35 V

AVDD1 to AVSS

−0.3 V to +66 V

AVDD2, VDPC+ to AGND, DGND

−0.3 V to +35 V

AVDD2, VDPC+ to AVSS

−0.3 V to +55 V

VLOGIC to DGND

−0.3 V to +6 V

Digital Inputs to DGND (SCLK,

SDI, SYNC, AD0, AD1, RESET,

LDAC)

−0.3 V to VLOGIC + 0.3 V or

+6 V (whichever is less)

Digital Outputs to DGND

(FAULT, SDO, CLKOUT)

−0.3 V to VLOGIC + 0.3 V or

+6 V (whichever is less)

REFIN, REFOUT, VLDO, CHART to

AGND

−0.3 V to AVDD2 + 0.3 V or

+6 V (whichever is less)

RA to AGND

−0.3 V to +4.5 V

RB to AGND

−0.3 V to +4.5 V

VIOUT to AGND

±38 V

+VSENSE to AGND

±38 V

−VSENSE to AGND

±38 V

ADC1, ADC2 to AGND

±38 V

CCOMP to AGND

AVSS − 0.3 V to VDPC+ + 0.3 V

SW+ to AGND

−0.3 V to AVDD1 + 0.3 V or

+33 V (whichever is less)

AGND, DGND to REFGND

−0.3 V to +0.3 V

AGND, DGND to PGND1

−0.3 V to +0.3 V

Industrial Operating

Temperature Range (TA)1

−40°C to +105°C

Storage Temperature Range

−65°C to +150°C

Junction Temperature

(TJ maximum)

125°C

Power Dissipation

(TJ maximum − TA)/θJA

Lead Temperature

JEDEC industry standard

Soldering

J-STD-020

Electrostatic Discharge (ESD)

Human Body Model2

±3 kV

Field Induced Charged

Device Model3

±1 kV

Power dissipated on chip must be derated to keep the junction temperature

below 125°C.

As per ANSI/ESDA/JEDEC JS-001, all pins.

As per ANSI/ESDA/JEDEC JS-002, all pins.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to

PCB thermal design is required. θJA is the junction to ambient

thermal resistance, and θJCis the junction to case thermal

resistance.

Table 5. Thermal Resistance

Package Type

θJA1

θJC

Unit

CP-32-30

°C/W

Test Condition 1: thermal impedance simulated values are based on a JEDEC 2S2P

thermal test board with thermal vias. See JEDEC JESD51.

ESD CAUTION

ADFS5758 Datasheet(PDF) 14 Page - Analog Devices

ADFS5758 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

Datasheet Download

Link URL