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ADFS5758 Datasheet(PDF) 39 Page - Analog Devices |
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ADFS5758 Datasheet(HTML) 39 Page - Analog Devices |
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39 / 75 page ![]() Data Sheet ADFS5758 Rev. 0 | Page 39 of 75 Bits[D31:D30] = 0b10 are used for synchronization purposes during readback. If autostatus readback mode is selected, the contents of the status register is available on the SDO line during every SPI transaction. This ability allows the user to continuously monitor the status register and act quickly in the case of a fault. The ADFS5758 powers up with this feature disabled. When this feature is enabled, the normal two-stage readback feature is not available. Only the status register is available on SDO. To read back any other register, disable the automatic readback feature first before following the two-stage readback sequence. The automatic status readback can be reenabled after the register is read back. The shared SYNC autostatus readback is a special version of the autostatus readback mode used to avoid SDO bus contention when multiple devices are sharing the same SYNC line. Echo mode behaves similarly to autostatus readback mode, except that every second readback consists of an echo of the previous command written to the ADFS5758 (see Figure 81). See the Reading from Registers section for further details on the readback modes. PREVIOUS COMMAND STATUS REGISTER CONTENTS PREVIOUS COMMAND Figure 81. SDO Contents, Echo Mode WINDOWED WATCHDOG TIMER (WDT) This watchdog timer feature is useful to ensure that communica- tion has not been lost between the system controller and the ADFS5758 and that the SPI datapath lines are functioning as expected. When enabled, the WDT alerts the system if the ADFS5758 does not receive a specific SPI frame in the user-programmable timeout period. A valid watchdog kick is a specific SPI frame received within the pass window of the WDT. When the specific SPI frame is received, the watchdog resets the timer controlling the timeout alert. The SPI frame used to reset the WDT is configurable as one of three choices: • A valid SPI write to any register. • A specific key code write to the key register (default). • Two specific consecutive key code writes to the key register. As shown in Figure 82, the watchdog timer uses a center threshold and a window width, where the width is a fraction of the center threshold. For example, if the center threshold is set to 100 ms and the window width set to 1/2, the valid region is 100 ms ± 25 ms. A WDT kick before 75 ms or after 125 ms is registered as a fault. The windowing feature of the WDT can be disabled by setting the window width to 1/1. In this scenario, the user must simply kick the WDT any time before the center threshold, eliminating the possibility of an early reset and thus simplifying the operation of the WDT. For highest safety, the window feature requires that the user write the correct key (or two keys, if enabled) within the timeout window. If the signal arrives before or after this timing window, the watchdog times out and a dedicated WDT_STATUS bit in the status register alerts the user that the WDT has timed out. The DIGITAL_DIAG_ RESULTS register can be read to clarify whether the WDT timeout was due to a late or early kick. Note that, when a WDT timeout occurs, all writes to the DAC_INPUT register as well as hardware or software LDAC events are ignored until the active WDT fault flag within the DIGITAL_DIAG_RESULTS register is cleared. Once this flag has been cleared the WDT can be restarted by performing a subsequent WDT kick command. On power-up, the WDT is disabled by default. The default settings of the center threshold and window width are 1 sec and 1/1, respectively. The default method to kick the WDT is to write one specific key and, upon timeout, the default action is to set the relevant flag bits and the FAULT pin. See Table 41 for specific register bit details to support the configurability of the WDT operation. USER DIGITAL OFFSET AND GAIN CONTROL The ADFS5758 has a USER_GAIN and a USER_OFFSET register that allow trimming of the gain and offset errors from the entire signal chain. The 16-bit USER_GAIN register allows the user to adjust the gain of the DAC channel in steps of 1 LSB. The USER_GAIN register coding is straight binary, as shown in Table 14. The default code in the USER_GAIN register is 0xFFFF, which results in no gain factor applied to the programmed output. In theory, the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy. Table 14. Gain Register Adjustment Gain Adjustment Factor D15 D14 to D1 D0 1 1 1 1 65,535/65,536 1 1 0 … … … … 2/65,536 0 0 1 1/65,536 0 0 0 CENTER THRESHOLD MUST RESET HERE FAULT: A RESET HERE IS TOO EARLY CENTER THRESHOLD – WINDOW WIDTH/2 CENTER THRESHOLD + WINDOW WIDTH/2 FAULT: RESET IS TOO LATE Figure 82. Windowed Watchdog Timer |
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