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SSM6515 Datasheet(PDF) 6 Page - Analog Devices |
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SSM6515 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 40 page  Data Sheet SSM6515 SPECIFICATIONS analog.com Rev. 0 | 6 of 40 Table 2. Digital Input/Output Parameter Min Typ Max Unit HIGH INPUT VOLTAGE (VIH) BCLK, FSYNC, SDATAI 0.7 × IOVDD 1.98 V SCL and SDA 0.7 × IOVDD 1.98 V LOW INPUT VOLTAGE (VIL) BCLK, FSYNC, SDATAI, SDA, SCL −0.3 +0.3 × IOVDD V INPUT LEAKAGE BCLK, FSYNC, SDATAI, SDA, SCL, ADDR High Input Current (IIH) 1 µA Low Input Current (IIL) 1 µA INPUT CAPACITANCE 5 pF TIMING SPECIFICATIONS Table 3. I2C Port Timing Parameter Min Max Unit Description I2C PORT fSCL 1 MHz SCL frequency tSCLH 0.26 µs SCL high tSCLL 0.5 µs SCL low tSCS 0.26 µs Setup time, relevant for repeated start condition tSCH 0.26 µs Hold time, after this period, the first clock is generated tDS 50 ns Data setup time tSCR 120 ns SCL rise time tSCF 120 ns SCL fall time tSDR 120 ns SDA rise time tSDF 120 ns SDA fall time tBFT 0.5 µs Bus-free time (time between stop and start) Table 4. Serial Port Digital Input Timing (I2S/TDM Operation Modes Only) Parameter Min Max Unit Description SERIAL PORT tBIL 8 ns BCLK low pulse width tBIH 8 ns BCLK high pulse width tSIS 4 ns SDATA setup time to BCLK rising edge tSIH 4 ns SDATA hold time from BCLK rising edge tLIS 5 ns FSYNC setup time to BCLK rising edge tLIH 5 ns FSYNC hold time to BCLK rising edge tBP 20 ns Minimum BCLK period dutyBCLK 40 60 % BCLK duty cycle Table 5. PDM Timing Parameters Parameter Limit Unit Description Min Max PDM Clock Frequency 2.8224 12.4 MHz tFALL 10 ns Clock fall time tRISE 10 ns Clock rise time tSETUP 10 ns Data setup time tHOLD 7 ns Data hold time |
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