SSM6515 datasheet(14/40 Pages) AD

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Data Sheet

SSM6515

THEORY OF OPERATION

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Rev. 0 | 14 of 40

OVERVIEW

The SSM6515 Class-D audio amplifier features a filterless, com-

mon-mode stable modulation scheme that reduces the external

component count, conserving board space and reducing system

cost. The SSM6515 does not require an output filter. It relies on

the inherent inductance of the speaker coil and the natural filtering

of the speaker and human ear to recover the audio component

of the square wave output. Most Class-D amplifiers use some

variation of pulse-width modulation (PWM), but the SSM6515 uses

Σ-Δ pulse-density modulation to determine the switching pattern of

the output devices, resulting in a number of important benefits. Σ-Δ

modulation reduces the amplitude of spectral components at high

frequencies, reducing EMI emission that can otherwise be radiated

by speakers and cable traces. In addition, the SSM6515 maintains

a stable common-mode output voltage that further reduces power

consumption, EMI, and filtering needed compared to other filterless

Class-D topologies.

The SSM6515 also integrates overcurrent protection that can be

disabled for lower power consumption. Overtemperature warnings

and protection are also integrated.

The SSM6515 supports two main modes of operation with control

and data supplied through the I2C and TDM/I2S ports (see Table

11) or PDM interface. A standalone mode of operation without I2C

control is also supported.

POWER SUPPLIES

PVDD is used for the main output stage, DAC, and Class-D modu-

lator. It is also used to generate a lower voltage purely internal core

supply.

IOVDD is used for the input signaling to set the high and low

voltage thresholds.

ADDR PIN SETUP AND CONTROL

The SSM6515 supports I2C control. The ADDR pin can be set to

four different levels: pulled to GND, pulled up to PVDD via a 47 kΩ

resistor, pulled down to ground via a 47 kΩ resistor, or left open.

The state of the ADDR pin determines the I2C device address or

if the device is in standalone mode. By default, in I2C mode, the

device uses the BCLK, FSYNC, and SDATAI pins for TDM/I2S data.

Alternatively, the device can be set to receive PDM data by setting

the PDM_MODE register bit field. See Table 11 for setting up the

desired mode.

Table 10. I2C Address Selection

ADDR Pin Connection

Control Port Mode

I2C Address

GND

I2C

0x34

Pull Down with 47 kΩ to GND

I2C

0x35

Open

I2C

0x36

Pull Up with 47 kΩ to PVDD

I2C

0x37

PVDD

Standalone mode

Not applicable

Table 11. Serial Port Mode Setup for I2S, TDM, and PDM

Serial Port Mode

Description

Pin Usage

BCLK Pin

FSYNC Pin

SDATAI Pin

I2S/TDM

Sets the device into default I2S/TDM mode

Bit clock input

Frame clock input

Data input I2S/TDM format

PDM

Set the PDM_MODE bit to 1 in Register 0x06

PDM clock input

Tie to GND

Data input PDM format

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