SSM6515 datasheet(20/40 Pages) AD

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Data Sheet

SSM6515

THEORY OF OPERATION

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Rev. 0 | 20 of 40

Addressing

Initially, each device on the I2C bus is in an idle state, monitoring

the SDA and SCL lines for a start condition and the proper address.

The I2C master initiates a data transfer by establishing a start

condition, defined by a high to low transition on SDA while SCL re-

mains high. This transition indicates that an address or data stream

follows. All devices on the bus respond to the start condition and

shift the next eight bits (the 7-bit address plus the R/W bit) MSB

first. The device that recognizes the transmitted address responds

by pulling the data line low during the ninth clock pulse. This ninth

bit is an acknowledge (ACK) bit. All other devices withdraw from the

bus at this point and return to the idle condition. The device address

for the SSM6515 is determined by the state of the ADDR pin. See

Table 14 for four available addresses.

The R/W bit determines the direction of the data. A Logic 0 on

the LSB of the first byte means the master writes information to

the peripheral, whereas a Logic 1 means that the master reads

information from the peripheral after writing the subaddress and

repeating the start address. A data transfer occurs until a stop con-

dition is encountered. A stop condition occurs when SDA transitions

from low to high while SCL is held high. The timing for the I2C port

is shown in Figure 35.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, the SSM6515 immediately jumps

to the idle condition. During a given SCL high period, the user must

issue only one start condition, one stop condition, or a single stop

condition followed by a single start condition. If the user issues an

invalid subaddress, the SSM6515 does not issue an acknowledge

and returns to the idle condition. If the user exceeds the highest

subaddress while in auto-increment mode, one of two actions is

taken.

In read mode, the SSM6515 outputs the highest subaddress reg-

ister contents until the master device issues a no acknowledge,

indicating the end of a read. A no acknowledge condition is when

the SDA line is not pulled low on the ninth clock pulse on SCL.

If the highest subaddress location is reached while in write mode,

the data for the invalid byte is not loaded into any subaddress

device returns to the idle condition.

Figure 35. I2C Read/Write Timing

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