Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SSM6515 Datasheet(PDF) 16 Page - Analog Devices

Part # SSM6515
Description  Ultra Low Power, Class-D Audio Amplifier
PDF  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

SSM6515 Datasheet(HTML) 16 Page - Analog Devices

Back Button SSM6515 Datasheet HTML 12Page - Analog Devices SSM6515 Datasheet HTML 13Page - Analog Devices SSM6515 Datasheet HTML 14Page - Analog Devices SSM6515 Datasheet HTML 15Page - Analog Devices SSM6515 Datasheet HTML 16Page - Analog Devices SSM6515 Datasheet HTML 17Page - Analog Devices SSM6515 Datasheet HTML 18Page - Analog Devices SSM6515 Datasheet HTML 19Page - Analog Devices SSM6515 Datasheet HTML 20Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 40 page
background image
Data Sheet
SSM6515
THEORY OF OPERATION
analog.com
Rev. 0 | 16 of 40
Table 13. BCLK_RATE Selection Table1, 2
LRCLK
(kHz)
BCLK_RATE: Bits[4:0] of Register Address 0x05
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
BCLK: FSYNC Ratio
83
N/A
256
400
500
512
600
768
800
1000
1024
1536
1600
2000
2048
3072
4000
4096
124
200
256
400
500
512
600
768
800
1000
1024
1536
1600
2000
2048
3072
4000
4096
163
N/A
128
200
250
256
300
384
400
500
512
768
800
1000
1024
1536
1600
2048
244
100
128
200
250
256
300
384
400
500
512
768
800
1000
1024
1536
1600
2048
323
N/A
64
100
125
128
150
192
200
250
256
384
400
500
512
768
800
1024
44.15
50
64
100
125
128
150
192
200
250
256
384
400
500
512
768
800
1024
485
50
64
100
125
128
150
192
200
250
256
384
400
500
512
768
800
1024
88.25
N/A
32
50
N/A
64
75
96
100
125
128
192
200
250
256
384
400
512
964
N/A
32
50
N/A
64
75
96
100
125
128
192
200
250
256
384
400
512
176.45
N/A
N/A
N/A
N/A
32
N/A
48
50
N/A
64
96
100
125
128
192
200
256
1924
N/A
N/A
N/A
N/A
32
N/A
48
50
N/A
64
96
100
125
128
192
200
256
3844
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
32
48
50
N/A
64
96
N/A
N/A
7684
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
32
48
N/A
N/A
1 Table 13 assumes a minimum of two channels.
2 N/A means not applicable.
3 32 kHz, 44.1 kHz, and 48 kHz are the sampling rates used to scale the ratio calculations for the SSM6515. 8 kHz and 16 kHz are scaled as 4x and 2x the 32 kHz settings,
respectively.
4 32 kHz, 44.1 kHz, and 48 kHz, are the sampling rates used to scale the ratio calculations for the SSM6515. 12 kHz, 24 kHz, 96 kHz, 192 kHz, 384 kHz, and 768 kHz are
scaled as 4x, 2x, 1/2, 1/4, 1/8, and 1/16 of the 48 kHz settings, respectively.
5 32 kHz, 44.1 kHz, and 48 kHz are the sampling rates used to scale the ratio calculations for the SSM6515. 88.2 kHz and 176.4 kHz are scaled as 1/2 and 1/4 of the 44.1
kHz settings, respectively.
STEREO (I2S/LEFT JUSTIFIED) OPERATING
MODE
Stereo modes use both edges of the FSYNC signal to determine
placement of data. Stereo mode is enabled when SPT_SAI_MODE
= 0, and the I2S or left justified format is determined by the
SPT_DATA_FORMAT register.
The I2S or left justified formats accepts any number of BCLK cycles
per FSYNC cycle as long as it is a supported BCLK rate.
Right justified operation can be achieved by using the delay by 8,
12, and 16 BCLK selections in the SPT_DATA_FORMAT register.
The amount of delay to achieve this is dependent on the number of
BCLK cycles per channel.
The SPT_SLOT_SEL register can select which channel of I2S is
routed to the DAC.
Sample rates from 8 kHz to 768 kHz are accepted.
TDM OPERATING MODE
The TDM operating mode allows more channels to use a single
serial interface bus.
The FSYNC signal operates at the desired sample rate. A rising
edge of the FSYNC signal indicates the start of a new frame.
Each chip on the TDM bus can occupy 16, 24, or 32 BCLK cycles.
This is set with the SPT_SLOT_WIDTH register and all chips on
the bus must have the same setting. Up to 32 SSM6515 chips can
be used on a single TDM bus, but only four unique I2C device
addresses are available. The SSM6515 automatically determines
how many possible chips can be placed on the bus from the BCLK
rate. There is no limit to the total number of BCLK cycles per
FSYNC pulse, except for the maximum 50 MHz frequency of BCLK.
The TDM slot data the SSM6515 device routes to the DAC is
determined by the SPT_SLOT_SEL bits.
PDM OPERATING MODE
By setting the PDM_MODE bit to 1, the DAC can be driven with
1-bit PDM data on SDATAI. In this case, a 2.8224 MHz to 3.072
MHz, 5.6448 MHz to 6.144 MHz, or 11.2896 MHz to 12.288 MHz
CLK must be provided on the BCLK pin. The frequency range is
selected via the PDM_FS register.
PDM input data is latched on both edges of the clock. The
PDM_CHAN_SEL register state determines which channel (CH0/
CH1) is sent to the DAC.
The PDM_PHASE_SEL register determines which two edges of
PDM_CLK are in phase, either falling then rising or rising then
falling.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com