SSM6515 datasheet(17/40 Pages) AD

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Data Sheet

SSM6515

THEORY OF OPERATION

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The amount of filtering on the PDM signal, and consequently the

input to output delay, is adjusted via the PDM_FILT register.

DIGITAL GAIN AND HIGH-PASS FILTER

There is a digital gain volume control in the DAC_VOL register

that provides fine control in 0.375 dB steps from −70 dB to +24

dB. The volume control can be bypassed to save additional power.

The volume control is bypassed by default. The DAC_VOL_MODE

setting is used to bypass the volume control with fixed gain of

either 0 dB or 6 dB or can enable the full selectable gain volume

control. Note that any DAC_VOL_MODE setting made after this

point overrides the fixed gain setting.

By default, the volume control ramps at a rate of 4.5 dB/ms

and only updates to a new value after a zero crossing. The soft

ramping can be disabled by setting DAC_HARD_VOL to 1. The

zero crossing can be disabled such that the volume control change

is instantaneous by setting DAC_VOL_ZC to 0.

Optional dc blocking is available and can be enabled via the

DAC_HPF_EN register. By default, this filter is disabled for lowest

power consumption. The corner frequency of this filter is variable

and can be set via the DAC_HPF_FC register.

OUTPUT LIMITER AND CLIPPER

The SSM6515 includes a digital output limiter. The limiter follows

the digital volume control in the signal chain. Therefore, the limiter

accounts for the gain setting of the volume control. By default, this

limiter is disabled to save power. It can be enabled by setting the

LIM_EN bit in the power control register to 1.

This is a peak limiter and its threshold to which it limits the output

is variable and set via the LIM_THRES register. Both the rate at

which the gain is reduced (the attack rate) and the rate at which the

gain is increased (the release rate) are determined by the LIM_RRT

For example, the limiter threshold is set to 0 dB by default. This

setting corresponds to 0 dB full-scale output, which is typically 1.15

V rms with 0 dBFS input at 1.8 V PVDD. If the volume control is

set to 0 dB and the limiter threshold is set to −10 dB, the limiter

activates at and above −10 dBFS input. That is, the output is limited

to −10 dB full scale (0.363 V rms).

If the volume control is set to 3 dB gain, the limiter activates at and

above −13 dBFS input, and the output is limited to −10 dB full scale

(0.363 V rms).

The SSM6515 output can also be digitally clipped, if desired, at a

level below the full-scale output. Clipping is symmetrical on both

the positive and negative output swings. The level at which clipping

occurs is determined by the DAC_HF_CLIP register. By default, the

clipper is set to 0 dB, which corresponds to no digital clipping.

The limiter block also offers the attack and release rate controls.

The attack rate is defined in μs/dB, whereas the release rate is

defined in ms/dB. For example, the attack rate determines the

attack time required for the limiter to start limiting the output when

above a set threshold. If the limiter threshold is set to −10 dB, with

an attack rate of 120 μs/dB and a release rate of 1600 ms/dB, and

the signal exceeds 5 dB above threshold or −5 dBFS, the limiter

takes approximately 120 μs/dB × 5 dB = 600 μs to start limiting the

output to −10 dB full scale. Similarly, the release rate determines

if the limiter releases the gain reduction when the input level falls

below the set threshold, such as −15 dBFS. Therefore, the limiter

releases the output in 1600 ms/dB × 5 dB = 8 sec to −15 dB full

scale.

Figure 30. Output Reference to Full Scale vs. Input, 0 dB Gain

Figure 31. Output Reference to Full Scale vs. Input, 3 dB Gain

FAULTS AND STATUS

The SSM6515 includes fault detection, protection, and status

reporting for amplifier over current fault, overtemperature fault,

and PVDD undervoltage fault. The device also detects and status

reports incorrect clocking ratios, incorrect serial port inputs, and an

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