SSM6515 datasheet(26/40 Pages) AD

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Data Sheet

SSM6515

analog.com

Rev. 0 | 26 of 40

MASTER AND BLOCK POWER CONTROL REGISTER

Address: 0x04, Reset: 0x01, Name: PWR_CTRL

Table 21. Bit Descriptions for PWR_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

RESERVED

Reserved.

0x0

LIM_EN

Limiter Enable.

0x0

R/W

Limiter disabled.

Limiter enabled.

[3:2]

RESERVED

Reserved.

0x0

APWDN_EN

Automatic Power-Down Enable. Automatic power-down automatically puts the IC in a low

power state when 2048 consecutive zero input samples are received.

0x0

R/W

Automatic power-down disabled.

Automatic power-down enabled.

SPWDN

Master Software Power-Down. Software power-down puts all blocks except the I2C interface

in a low power state.

0x1

R/W

Normal operation.

Software master power-down.

BCLK RATE CONTROL REGISTER

Address: 0x05, Reset: 0x00, Name: CLK_CTRL

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