SSM6515 datasheet(28/40 Pages) AD

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Data Sheet

SSM6515

analog.com

Rev. 0 | 28 of 40

Table 23. Bit Descriptions for PDM_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

[5:4]

PDM_FILT

PDM Input Filtering Control.

0x2

R/W

Highest filtering. Highest latency.

Medium filtering. Medium latency.

Lowest filtering. Lowest latency.

PDM_CHAN_SEL

PDM Channel Select.

0x0

R/W

PDM rising edge channel used.

PDM falling edge channel used.

[2:1]

PDM_FS

PDM Sample Rate Selection.

0x0

R/W

5.6448 MHz to 6.144 MHz clock in PDM mode.

2.8224 MHz to 3.072 MHz clock in PDM mode.

11.2896 MHz to 12.288 MHz clock in PDM mode.

PDM_MODE

PDM or PCM Input Mode.

0x0

R/W

Normal PCM/SAI operation.

PDM used for input.

DAC SAMPLE RATE, POWER MODES, FILTERING CONTROLS REGISTER

Address: 0x07, Reset: 0x15, Name: DAC_CTRL1

Table 24. Bit Descriptions for DAC_CTRL1

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

DAC_IBIAS

DAC Bias Control.

0x0

R/W

Normal operation.

Power saving.

Improved performance.

Reserved.

[5:4]

DAC_PWR_MODE

DAC Power Mode.

0x1

R/W

No power savings.

Power savings mode.

Most power savings mode (1 μs additional latency).

[3:0]

DAC_FS

DAC Path Sample Rate Selection.

0x5

R/W

0000

8 kHz sample rate.

0001

12 kHz sample rate.

0010

16 kHz sample rate.

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