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SSM6515 Datasheet(PDF) 27 Page - Analog Devices |
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SSM6515 Datasheet(HTML) 27 Page - Analog Devices |
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27 / 40 page ![]() Data Sheet SSM6515 REGISTER DETAILS: I2C REGISTER MAP analog.com Rev. 0 | 27 of 40 Table 22. Bit Descriptions for CLK_CTRL Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved. 0x0 R [4:0] BCLK_RATE BCLK Clock Rate Selection. 0x0 R/W 00000 Automatic BCLK rate detection. 00001 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 00010 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 00011 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 00100 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 00101 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 00110 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 00111 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 01000 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 01001 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 01010 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 01011 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 01100 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 01101 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 01110 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 01111 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 10000 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. 10001 Refer to the Pulse Code Modulation (PCM) Digital Audio Serial Interface section. PDM CONTROL REGISTER Address: 0x06, Reset: 0x20, Name: PDM_CTRL Table 23. Bit Descriptions for PDM_CTRL Bits Bit Name Settings Description Reset Access 7 PDM_PHASE_SEL PDM Phase Select. 0x0 R/W 0 Fall-rise channel pair is in phase. 1 Rise-fall channel pair is in phase. 6 RESERVED Reserved. 0x0 R |
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