CS47L85 datasheet(120/370 Pages) CIRRUS

120 / 370 page

CS47L85

120

Rev 4.3

ISOCHRONOUS SAMPLE RATE CONVERTER (ISRC)

The CS47L85 supports multiple signal paths through the digital core. The Isochronous Sample Rate Converters (ISRCs)

provide sample rate conversion between synchronised sample rates on the SYSCLK clock domain, or between synchronised

sample rates on the ASYNCCLK clock domain.

There are four Isochronous Sample Rate Converters (ISRCs). ISRC1 and ISRC2 provide four signal paths between two

different sample rates; ISRC3 and ISRC4 provide two signal paths between two different sample rates, as illustrated in

Figure 39.

The sample rates associated with each ISRC can be set independently. Note that the two sample rates associated with any

single ISRC must both be referenced to the same clock domain (SYSCLK or ASYNCCLK).

When an ISRC is used on the SYSCLK domain, then the associated sample rates may be selected from SAMPLE_RATE_1,

SAMPLE_RATE_2 or SAMPLE_RATE_3.

When an ISRC is used on the ASYNCCLK domain, then the associated sample rates are ASYNC_SAMPLE_RATE_1 and

ASYNC_SAMPLE_RATE_2.

See “Clocking and Sample Rates” for details of the sample rate control registers.

Each ISRC supports sample rates in the range 8kHz to 192kHz. The higher of the sample rates associated with each ISRC

must be an integer multiple of the lower sample rate; all possible integer ratios are supported (i.e., up to 24).

Each ISRC converts between a sample rate selected by ISRCn_FSL and a sample rate selected by ISRCn_FSH, (where ‘n’

identifies the applicable ISRC 1, 2, 3 or 4). Note that, in each case, the higher of the two sample rates must be selected by

ISRCn_FSH.

The ISRCn_FSL and ISRCn_FSH registers should not be changed if any of the respective *_SRCn registers is non-zero.

The associated *_SRCn registers should be cleared to 00h before writing new values to ISRCn_FSL or ISRCn_FSH. A

minimum delay of 125us should be allowed between clearing the *_SRCn registers and writing to the associated ISRCn_FSL

or ISRCn_FSH registers. See Table 24 for further details.

The ISRCn

‘interpolation’ paths (increasing sample rate) are enabled using the ISRCn_INTm_ENA register bits, (where ‘m’

identifies the applicable channel).

The ISRCn

‘decimation’ paths (decreasing sample rate) are enabled using the ISRCn_DECm_ENA register bits.

The CS47L85 performs automatic checks to confirm that the SYSCLK or ASYNCCLK frequency is high enough to support

the commanded ISRC and digital mixing functions. If an attempt is made to enable an ISRC signal path, and there are

insufficient SYSCLK or ASYNCCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths

that are already active will not be affected under these circumstances.)

The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error

condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled.

The Isochronous Sample Rate Converter (ISRC) signal paths and control registers are illustrated in Figure 39.

CS47L85 Datasheet(PDF) 120 Page - Cirrus Logic