CS47L85 datasheet(122/370 Pages) CIRRUS

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CS47L85

122

Rev 4.3

The ISRC input control registers (see Figure 39) are located at register addresses R2816 (B00h) through to R3015 (0BC7h).

The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see

“Register Map” for further information. Generic register definitions are provided in Table 8.

The *_SRC registers select the input source(s) for the respective ISRC processing blocks. Note that the selected input

source(s) must be configured for the same sample rate as the ISRC to which they are connected.

The bracketed numbers in Figure 39,

e.g.,”(A4h)” indicate the corresponding *_SRC register setting for selection of that

signal as an input to another digital core function.

The ISRC paths should be kept disabled (ISRCn_INTm_ENA=0, ISRCn_DECm_ENA=0) if SYSCLK is not enabled. The

*_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present

and enabled before select

ing other values for these registers. See “Clocking and Sample Rates” for further details (including

requirements for reconfiguring SYSCLK while digital core functions are enabled).

The register bits associated with the ISRCs are described in Table 24.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3824

(0EF0h)

ISRC1_CT

RL_1

14:11

ISRC1_FSH [3:0]

0000

ISRC1 High Sample Rate

(Sets the higher of the ISRC1 sample

rates)

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

1000 = ASYNC_SAMPLE_RATE_1

1001 = ASYNC_SAMPLE_RATE_2

All other codes are Reserved.

The selected sample rate is valid in the

range 8kHz to 192kHz.

The ISRC1_FSH and ISRC1_FSL fields

must both select sample rates referenced

to the same clock domain (SYSCLK or

ASYNCCLK).

All ISRC1_DECn_SRC registers should

be set to 00h before changing

ISRC1_FSH.

R3825

(0EF1h)

ISRC1_CT

RL_2

14:11

ISRC1_FSL [3:0]

0000

ISRC1 Low Sample Rate

(Sets the lower of the ISRC1 sample

rates)

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

1000 = ASYNC_SAMPLE_RATE_1

1001 = ASYNC_SAMPLE_RATE_2

All other codes are Reserved.

The selected sample rate is valid in the

range 8kHz to 192kHz.

The ISRC1_FSH and ISRC1_FSL fields

must both select sample rates referenced

to the same clock domain (SYSCLK or

ASYNCCLK).

All ISRC1_INTn_SRC registers should be

set to 00h before changing ISRC1_FSL.

R3826

(0EF2h)

ISRC1_CT

RL_3

ISRC1_INT1_EN

ISRC1 INT1 Enable

(Interpolation Channel 1 path from

ISRC1_FSL rate to ISRC1_FSH rate)

0 = Disabled

1 = Enabled

ISRC1_INT2_EN

ISRC1 INT2 Enable

(Interpolation Channel 2 path from

ISRC1_FSL rate to ISRC1_FSH rate)

0 = Disabled

1 = Enabled

CS47L85 Datasheet(PDF) 122 Page - Cirrus Logic

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