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CS47L85 Datasheet(PDF) 125 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 125 Page - Cirrus Logic |
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125 / 370 page  CS47L85 Rev 4.3 125 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3830 (0EF6h) ISRC3_CT RL_1 14:11 ISRC3_FSH [3:0] 0000 ISRC3 High Sample Rate (Sets the higher of the ISRC3 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC3_FSH and ISRC3_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC3_DECn_SRC registers should be set to 00h before changing ISRC3_FSH. R3831 (0EF7h) ISRC3_CT RL_2 14:11 ISRC3_FSL [3:0] 0000 ISRC3 Low Sample Rate (Sets the lower of the ISRC3 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC3_FSH and ISRC3_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC3_INTn_SRC registers should be set to 00h before changing ISRC3_FSL. R3832 (0EF8h) ISRC3_CT RL_3 15 ISRC3_INT1_EN A 0 ISRC3 INT1 Enable (Interpolation Channel 1 path from ISRC3_FSL rate to ISRC3_FSH rate) 0 = Disabled 1 = Enabled 14 ISRC3_INT2_EN A 0 ISRC3 INT2 Enable (Interpolation Channel 2 path from ISRC3_FSL rate to ISRC3_FSH rate) 0 = Disabled 1 = Enabled 9 ISRC3_DEC1_EN A 0 ISRC3 DEC1 Enable (Decimation Channel 1 path from ISRC3_FSH rate to ISRC3_FSL rate) 0 = Disabled 1 = Enabled 8 ISRC3_DEC2_EN A 0 ISRC3 DEC2 Enable (Decimation Channel 2 path from ISRC3_FSH rate to ISRC3_FSL rate) 0 = Disabled 1 = Enabled |
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