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CS47L85 Datasheet(PDF) 126 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 126 Page - Cirrus Logic |
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126 / 370 page ![]() CS47L85 126 Rev 4.3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3833 (0EF9h) ISRC4_CT RL_1 14:11 ISRC4_FSH [3:0] 0000 ISRC4 High Sample Rate (Sets the higher of the ISRC4 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC4_FSH and ISRC4_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC4_DECn_SRC registers should be set to 00h before changing ISRC4_FSH. R3834 (0EFAh) ISRC4_CT RL_2 14:11 ISRC4_FSL [3:0] 0000 ISRC4 Low Sample Rate (Sets the lower of the ISRC4 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC4_FSH and ISRC4_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC4_INTn_SRC registers should be set to 00h before changing ISRC4_FSL. R3835 (0EFBh) ISRC4_CT RL_3 15 ISRC4_INT1_EN A 0 ISRC4 INT1 Enable (Interpolation Channel 1 path from ISRC4_FSL rate to ISRC4_FSH rate) 0 = Disabled 1 = Enabled 14 ISRC4_INT2_EN A 0 ISRC4 INT2 Enable (Interpolation Channel 2 path from ISRC4_FSL rate to ISRC4_FSH rate) 0 = Disabled 1 = Enabled 9 ISRC4_DEC1_EN A 0 ISRC4 DEC1 Enable (Decimation Channel 1 path from ISRC4_FSH rate to ISRC4_FSL rate) 0 = Disabled 1 = Enabled 8 ISRC4_DEC2_EN A 0 ISRC4 DEC2 Enable (Decimation Channel 2 path from ISRC4_FSH rate to ISRC4_FSL rate) 0 = Disabled 1 = Enabled Table 24 Digital Core ISRC Control |
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