CS47L85 datasheet(130/370 Pages) CIRRUS

130 / 370 page

CS47L85

130

Rev 4.3

BIT

LABEL

DEFAULT

DESCRIPTION

DSP1 Base Address = R1048064 (0FFE00h)

DSP2 Base Address = R1572352 (17FE00h)

DSP3 Base Address = R2096640 (1FFE00h)

DSP4 Base Address = R2620928 (27FE00h)

DSP5 Base Address = R3145216 (2FFE00h)

DSP6 Base Address = R3669504 (37FE00h)

DSP7 Base Address = R4193792 (3FFE00h)

base address + 54h

DSPn_Ext_window_A

DSPn_EXT_A_PSIZE16

0 = 32-bit

1 = 16-bit

Note that, in 32-bit mode, only the

lower 24 bits can be accessed.

15:0

DSPn_EXT_A_PAGE [15:0]

0000h

Sets the Base Address of Register

Window A in X-Memory.

Coded as LSB = 512 (200h)

base address + 56h

DSPn_Ext_window_B

DSPn_EXT_B_PSIZE16

0 = 32-bit

1 = 16-bit

Note that, in 32-bit mode, only the

lower 24 bits can be accessed.

15:0

DSPn_EXT_B_PAGE [15:0]

0000h

Sets the Base Address of Register

Window B in X-Memory.

Coded as LSB = 512 (200h)

base address + 58h

DSPn_Ext_window_C

DSPn_EXT_C_PSIZE16

0 = 32-bit

1 = 16-bit

Note that, in 32-bit mode, only the

lower 24 bits can be accessed.

15:0

DSPn_EXT_C_PAGE [15:0]

0000h

Sets the Base Address of Register

Window C in X-Memory.

Coded as LSB = 512 (200h)

base address + 5Ah

DSPn_Ext_window_D

DSPn_EXT_D_PSIZE16

0 = 32-bit

1 = 16-bit

Note that, in 32-bit mode, only the

lower 24 bits can be accessed.

15:0

DSPn_EXT_D_PAGE [15:0]

0000h

Sets the Base Address of Register

Window D in X-Memory.

Coded as LSB = 512 (200h)

Table 26 X Data Memory Window Control

DSP FIRMWARE CONTROL

The DSP memory (Program, Coefficient, X-Data, and Y-Data) is enabled using the DSPn_MEM_ENA register bit for the

respective DSP. This memory must be enabled (DSPn_MEM_ENA=1) for read/write access, code execution, and DMA

functions. The DSP memory is disabled, and the contents lost, whenever the respective DSPn_MEM_ENA bit is set to 0.

The DSP6_MEM_ENA bit has no function; the DSP6 memory is enabled at all times during normal operation.

The DSPn_MEM_ENA bits are not affected by Software Reset; these bits will remain in their previous state under Software

Reset conditions. Accordingly, the DSP memory contents will be maintained through Software Reset, provided DCVDD is

held above its reset threshold.

On DSP1 to DSP5, and on DSP7, the DSP firmware memory is cleared under Hardware Reset conditions. For DSP6 only,

the contents of the DSP memory are retained during Hardware Reset, provided DCVDD is held above its reset threshold.

The DSP firmware memory is always cleared under Power-

On Reset (POR), and ‘Sleep’ mode conditions. See the

“Applications Information” section for a summary of the CS47L85 reset behaviour.

Clocking is required for each of the DSP processing blocks, when executing software or when supporting DMA functions.

(Note that clocking is not required for access to the firmware registers by the host processor.)

CS47L85 Datasheet(PDF) 130 Page - Cirrus Logic

CS47L85 Datasheet(HTML) 130 Page - Cirrus Logic

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