CS47L85 datasheet(131/370 Pages) CIRRUS

131 / 370 page

CS47L85

Rev 4.3

131

Clocking within each DSP is enabled and disabled automatically, as required by the respective DSP Core and DMA channel

status.

The clock source for each DSP is derived from DSPCLK. See “Clocking and Sample Rates” for details of how to configure

DSPCLK.

The clock frequency for each DSP is selected using the DSPn_CLK_SEL register (where ‘n’ identifies the applicable DSP

block, 1 to 7). The DSP clock frequency must be less than or equal to the DSPCLK frequency. For DSP6 and DSP7, the

maximum DSP clock frequency is 75MHz.

Note that the DSPn_CLK_SEL fields select a range of frequencies for each valid decode value. The clock frequency for

each DSP will be derived as DSPCLK divided by 1, 2, 4, 8, or 16. The required division ratios, within the selected DSP clock

frequency ranges, are configured automatically for each DSP core.

The DSPn_CLK_SEL_STS fields provide readback of the clock frequency range for the respective DSP cores. These can

be used to confirm the clock frequency, in cases where code execution has a minimum clock frequency requirement. The

DSPn_CLK_SEL_STS field is only valid when the respective core is running code; typical usage of this field would be for

the DSP core itself to readback the clock status, and to take action as applicable (in particular, if the available clock does

not meet the application requirements).

Note that the DSPn_CLK_SEL_STS fields indicate a range of frequencies for each decode value. The exact clock frequency

for each DSP cannot be provided directly by the CS47L85, but can be derived using knowledge of the DSPCLK frequency,

if available.

After the DSP firmware has been loaded, and the clocks configured, the DSP blocks are enabled using the

DSPn_CORE_ENA register bits. When the DSP is configured and enabled, the firmware execution can be started by writing

‘1’ to the respective DSPn_START bit.

Alternative methods to trigger the firmware execution can also be configured using the DSPn_START_IN_SEL register fields.

Note that this provides the capability to synchronously trigger multiple DSP blocks.

Using the DSPn_START_IN_SEL registers, the DSP firmware execution can be linked to the respective DMA function, the

IRQ2 status, ‘DSPn Start’ signals from another DSP, or to the FIFO status in one of the Event Loggers:



DMA function - firmware execution commences when all enabled DSP input (WDMA) channel buffers have been

filled, and all enabled DSP output (RDMA) channel buffers have been emptied



DSPn Start signals - firmware execution commences when the respective Start signal is triggered in the selected

DSP core (1 to 4 only)



IRQ2 - firmware execution commences when one or more of the unmasked IRQ2 events has occurred



Event Logger status -

firmware execution commences when the FIFO ‘Not Empty’ status is asserted within the

respective Event Logger

The DSPn_CORE_ENA bit must be set to ‘1’ to enable firmware execution on the respective DSP block. Note that the usage

of the DSPn_START bit may vary depending on the particular firmware that is being executed: in some applications (e.g.,

when an alternative trigger is selected using DSPn_START_IN_SEL), writing to the DSPn_START bit will not be required.

The DSPCLK system clock must be configured and enabled before any DSP processing core is enabled. The DSP blocks

should be kept disabled (DSPn_CORE_ENA=0) if DSPCLK is not enabled. See “Clocking and Sample Rates” for details of

the system clocks (including requirements for reconfiguring DSPCLK while DSP cores are enabled).

The audio signal paths connecting to/from the DSP processing blocks are configured as described in the “Digital Core”

section. Note that the DSP firmware must be loaded and enabled before audio signal paths can be enabled.

The DSP memory and clocking control registers are described in Table 27.

CS47L85 Datasheet(PDF) 131 Page - Cirrus Logic

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