CS47L85 datasheet(133/370 Pages) CIRRUS

133 / 370 page

CS47L85

Rev 4.3

133

BIT

LABEL

DEFAULT

DESCRIPTION

3:1

DSPn_CLK_SEL_STS [2:0]

000

DSPn Clock Frequency

(Read only, Only valid when the

respective DSP Core is enabled)

000=5.5MHz to 9.375MHz

001=9.375MHz to 18.75MHz

010=18.75MHz to 37.5MHz

011=37.5MHz to 75MHz

100=75MHz to 150MHz

All other codes are Reserved

Note that, because DSPCLK could be

any frequency (within the valid

ranges), it is not possible to quote

exact frequencies in this register

definition. The exact frequency will be

derived as DSPCLK divided by 1, 2, 4,

8, or 16.

DSPn_CLK_AVAIL

DSPn Clock Availability

(Read only)

0 = No Clock

1 = Clock Available

Note

– this bit exists for legacy

software support only; it is not

recommended for future designs, as

the readback may be unreliable on the

latest device architectures.

base address +38h

DSPn_External_Start

4:0

DSPn_START_IN_SEL [4:0]

00h

DSPn Firmware Execution control

Selects the trigger for DSPn firmware

execution.

00h = DMA

01h = DSP1 Start 1

02h = DSP1 Start 1

03h = DSP2 Start 1

04h = DSP2 Start 2

05h = DSP3 Start 1

06h = DSP3 Start 2

07h = DSP4 Start 1

08h = DSP4 Start 2

0Bh = IRQ2

10h = Event Logger 1

11h = Event Logger 2

12h = Event Logger 3

13h = Event Logger 4

14h = Event Logger 5

15h = Event Logger 6

16h = Event Logger 7

17h = Event Logger 8

All other codes are Reserved.

Note that the DSPn_START bit will

also start the DSPn firmware

execution, regardless of this register

setting.

Table 27 DSP Memory and Clocking Control

CS47L85 Datasheet(PDF) 133 Page - Cirrus Logic

CS47L85 Datasheet(HTML) 133 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL