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CS47L85 Datasheet(PDF) 137 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 137 Page - Cirrus Logic |
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137 / 370 page  CS47L85 Rev 4.3 137 DSP INTERRUPTS The DSP cores provide inputs to the Interrupt circuit, and can be used to trigger an Interrupt event when the associated conditions occur. For each DSP, the following Interrupts are provided: DMA Interrupt - asserted when all enabled DSP input (WDMA) channel buffers have been filled, and all enabled DSP output (RDMA) channel buffers have been emptied DSP Start 1, DSP Start 2 Interrupts - asserted when the respective Start signal is triggered DSP Busy Interrupt - asserted when the DSP is busy (i.e., when firmware execution or DMA processes are started) The CS47L85 also provides 16 control bits that allow the DSP cores to generate programmable Interrupt events. When a ‘1’ is written to these bits (see Table 29), the respective DSP Interrupt (DSP_IRQn_EINTx) will be triggered. The associated Interrupt bits are latched once set; they can be polled at any time, or used to control the IRQ signal. See “Interrupts” for further details. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5632 (1600h) ADSP2_IR Q0 1 DSP_IRQ2 0 DSP IRQ2 Write ‘1’ to trigger the DSP_IRQ2_EINTn interrupt. 0 DSP_IRQ1 0 DSP IRQ1 Write ‘1’ to trigger the DSP_IRQ1_EINTn interrupt. R5633 (1601h) ADSP2_IR Q1 1 DSP_IRQ4 0 DSP IRQ4 Write ‘1’ to trigger the DSP_IRQ4_EINTn interrupt. 0 DSP_IRQ3 0 DSP IRQ3 Write ‘1’ to trigger the DSP_IRQ3_EINTn interrupt. R5634 (1602h) ADSP2_IR Q2 1 DSP_IRQ6 0 DSP IRQ6 Write ‘1’ to trigger the DSP_IRQ6_EINTn interrupt. 0 DSP_IRQ5 0 DSP IRQ5 Write ‘1’ to trigger the DSP_IRQ5_EINTn interrupt. R5635 (1603h) ADSP2_IR Q3 1 DSP_IRQ8 0 DSP IRQ8 Write ‘1’ to trigger the DSP_IRQ8_EINTn interrupt. 0 DSP_IRQ7 0 DSP IRQ7 Write ‘1’ to trigger the DSP_IRQ7_EINTn interrupt. R5636 (1604h) ADSP2_IR Q4 1 DSP_IRQ10 0 DSP IRQ10 Write ‘1’ to trigger the DSP_IRQ10_EINTn interrupt. 0 DSP_IRQ9 0 DSP IRQ9 Write ‘1’ to trigger the DSP_IRQ9_EINTn interrupt. R5637 (1605h) ADSP2_IR Q5 1 DSP_IRQ12 0 DSP IRQ12 Write ‘1’ to trigger the DSP_IRQ12_EINTn interrupt. 0 DSP_IRQ11 0 DSP IRQ11 Write ‘1’ to trigger the DSP_IRQ11_EINTn interrupt. R5638 (1606h) ADSP2_IR Q6 1 DSP_IRQ14 0 DSP IRQ14 Write ‘1’ to trigger the DSP_IRQ14_EINTn interrupt. 0 DSP_IRQ13 0 DSP IRQ13 Write ‘1’ to trigger the DSP_IRQ13_EINTn interrupt. |
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