CS47L85 datasheet(141/370 Pages) CIRRUS

141 / 370 page

CS47L85

Rev 4.3

141

The DSPCLK system clock must be configured and enabled before a Master Interface transaction is scheduled. The Master

Interfaces should be kept idle

if DSPCLK is not enabled. See “Clocking and Sample Rates” for details of the system clocks

(including requirements for reconfiguring DSPCLK while DSP peripherals are enabled).

The MIFn_BUSY_STS bit indicates when the Master Interface is executing an I2C transaction. This bit is set high during

each I2C transaction, and set low on completion. An Interrupt event is also triggered on completion of the I2C transfer, if the

corresponding MIFn_DONE_EINTx is unmasked as an input to the IRQ circuit.

Additional status bits are provided to indicate Watchdog Timeout, or a NACK error signal received. See Table 32 for further

details of these bits.

Note that the ‘MIF DONE’ indication described above will be asserted each time an I2C transfer completes, including when

an error condition has occurred. It is recommended that the Master Interface status bits be checked after each I2C

transaction, in order that corrective action can be taken when necessary.

The external connections associated with each I2C Master Interface (MIF) are implemented on multi-function GPIO pins,

which must be configured for the respective MIF functions when required. The MIFnSCLK and MIFnSDA connections are

pin-

specific alternative functions available on specific GPIO pins. See “General Purpose Input / Output” to configure the

GPIO pins for the MIF operation.

The Master Interface provides inputs to the Interrupt control circuit. An interrupt event is triggered on completion of each

TX/RX Block, and on completion of the I2C transaction -

see “Interrupts”.

Typical Master I2C transfers are illustrated in Figure 41 through to Figure 43.

SDA

SCLK

Device Address

MIFn_SLV_ADDR

R/W

Write Data bits

MIFn_TX_BUFx_BYTEy

Write Data bits

MIFn_TX_BUFx_BYTEy

ACK

(Write)

ACK

START

STOP

Blue = Initiated by I2C Master

Purple = Initiated by I2C Slave

Figure 41 Master I2C Write

Read Data bits

MIFn_RX_BUFx_BYTEy

ACK

R/W

Read Data bits

MIFn_RX_BUFx_BYTEy

ACK

STOP

ACK

SDA

SCLK

Device Address

MIFn_SLV_ADDR

(Read)

START

(NACK)

Blue = Initiated by I2C Master

Purple = Initiated by I2C Slave

Figure 42 Master I2C Read

SDA

SCLK

Device Address

MIFn_SLV_ADDR

Device Address

MIFn_SLV_ADDR

R/W

Write Data bits

MIFn_TX_BUFx_BYTEy

Read Data bits

MIFn_RX_BUFx_BYTEy

START

(Write)

ACK

R/W

(Read)

STOP

ACK

Rpt

START

Figure 43 Master I2C Write & Read

CS47L85 Datasheet(PDF) 141 Page - Cirrus Logic

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