CS47L85 datasheet(144/370 Pages) CIRRUS

144 / 370 page

CS47L85

144

Rev 4.3

BIT

LABEL

DEFAULT

DESCRIPTION

base address +110h

MIFn_CONFIG_5

20:0

MIFn_RX_LENGTH [20:0]

00_0000h

Selects the total number of data

bytes in an I2C Read operation.

00_0000h = 1 byte

00_0001h = 2 bytes

00_0002h = 3 bytes

…

1F_FFFFh = 2,097,152 bytes

base address +112h

MIFn_CONFIG_6

7:0

MIFn_TX_BLOCK_LENGTH

[7:0]

10h

Selects the interval at which the

MIFn_BLOCK Interrupt is triggered

during I2C Write operations.

00h = 1 byte

01h = 1 byte

02h = 2 bytes

…

10h = 16 bytes

All other codes are Reserved

base address +114h

MIFn_CONFIG_7

7:0

MIFn_RX_BLOCK_LENGTH

[7:0]

10h

Selects the interval at which the

MIFn_BLOCK Interrupt is triggered

during I2C Read operations.

00h = 1 byte

01h = 1 byte

02h = 2 bytes

…

10h = 16 bytes

All other codes are Reserved

base address +116h

MIFn_CONFIG_8

MIFn_RX_DONE

RX Buffer access control bit

Write ‘1’ to indicate that data in the

RX Buffer has been read.

In normal operation, a ‘1’ is written

after reading the RX buffer. This

causes the MIFn_RX_REQUEST bit

to be reset to ‘0’. (Note that, if further

data is available to read, then the

MIFn_RX_REQUEST bit will remain

set in this case.)

MIFn_TX_DONE

TX Buffer access control bit

Write ‘1’ to indicate the TX Buffer has

been filled with data for transmission.

In normal operation, a ‘1’ is written

after writing the TX buffer. This

causes the MIFn_TX_REQUEST bit

to be reset to ‘0’.

base address +180h

MIFn_STATUS_1

MIFn_BUSY_STS

MIF Busy Status.

This bit, when set, indicates that the

Master Interface is executing an I2C

transaction.

MIFn_RX_REQUEST

RX Buffer flow control bit

0 = No data available to read

1 = Buffer data is available to read

MIFn_TX_REQUEST

TX Buffer flow control bit

0 = TX buffer not available to write

1 = TX buffer is available to write

base address +182h

MIFn_STATUS_2

20:0

MIFn_BYTE_COUNT [20:0]

00_0000h

Number of data bytes transferred in

current transaction.

Note that this field is cleared on

completion of the I2C transaction.

base address +200h

MIFn_TX_1

31:24

MIFn_TX_BYTE4 [7:0]

00h

TX Byte 4

23:16

MIFn_TX_BYTE3 [7:0]

00h

TX Byte 3

15:8

MIFn_TX_BYTE2 [7:0]

00h

TX Byte 2

7:0

MIFn_TX_BYTE1 [7:0]

00h

TX Byte 1

CS47L85 Datasheet(PDF) 144 Page - Cirrus Logic

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