CS47L85 datasheet(142/370 Pages) CIRRUS

142 / 370 page

CS47L85

142

Rev 4.3

The MIF control registers are described in Table 32.

BIT

LABEL

DEFAULT

DESCRIPTION

MIF1 Base Address = R262144 (40000h)

MIF2 Base Address = R263168 (40400h)

MIF3 Base Address = R264192 (40800h)

base address +002h

MIFn_I2C_CONFIG_2

10:1

MIFn_SLV_ADDR [9:0]

000h

Address of Slave on which

transactions are executed.

For 7-bit mode, lower 7 bits of field

are used.

MIFn_ADDR_MODE

Selects the addressing mode of I2C

Master

0= 7-bit mode

1= 10-bit mode

base address +004h

MIFn_I2C_CONFIG_3

MIFn_NACK_RESPONSE

Selects the action taken if NACK is

received from Slave.

0 = Stop Condition sent.

1 = Stop Condition not sent; next

transaction will commence with a

Repeated Start.

Note that, if the Stop Condition is not

sent, the Master retains control of the

bus until a subsequent action is

scheduled. The next transaction will

commence with a Repeated Start in

this case.

MIFn_SCL_MON_ENA

Enables bus monitoring functions on

SCLK

0 = Disabled

1 = Enabled

This feature enables support for

clock stretching by Slave devices,

and enables Bus Synchronisation as

part of multi-master operation.

MIFn_RPT_START

Selects the action taken on

completion of a bus transaction.

0 = Stop Condition sent.

1 = Stop Condition not sent; next

transaction will commence with a

Repeated Start.

Note that, if the Stop Condition is not

sent, the Master retains control of the

bus until a subsequent action is

scheduled. The next transaction will

commence with a Repeated Start in

this case.

MIFn_START_BYTE_ENA

Selects whether a Start Byte is

transmitted before an I2C

transaction.

0 = Disabled

1 = Enabled

The Start Byte is a dummy

transaction that provides support for

bus devices that use low-frequency

polling to detect I2C activity. The

Start Byte, when enabled, is

transmitted before the Slave Address

byte(s). It is not acknowledged on the

bus by any device.

CS47L85 Datasheet(PDF) 142 Page - Cirrus Logic

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