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CS47L85 Datasheet(PDF) 143 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 143 Page - Cirrus Logic |
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143 / 370 page ![]() CS47L85 Rev 4.3 143 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION base address +008h MIFn_I2C_CONFIG_5 0 MIFn_WDT_ENA 0 Watchdog Timer (WDT) control 0 = Disabled 1 = Enabled When bus monitoring functions are enabled (MIFn_SCL_MON_ENA=1), the Watchdog Timer is used to detect the SCLK line being pulled low for a prolonged duration. base address +080h MIFn_I2C_STATUS_1 2 MIFn_WDT_TIMEOUT_STS 0 Watchdog Timer (WDT) Error Status This bit, when set, indicates that the WDT expired during the I2C transaction. This bit is latched when set; it is cleared by writing ‘1’. This bit is automatically cleared on next I2C transaction. 0 MIFn_NACK_STS 0 NACK Error Status This bit, when set, indicates that a NACK Error signal was received during the I2C transaction. This bit is latched when set; it is cleared by writing ‘1’. This bit is automatically cleared on next I2C transaction. base address +100h MIFn_CONFIG_1 0 MIFn_START 0 Starts the I2C transaction Write ‘1’ to start. base address +104h MIFn_CONFIG_3 17:16 MIFn_WORD_SIZE [1:0] 00 Selects the data word format. I2C transactions are made up of 1- Byte data words; the sequence order of these words differs according to the applicable word format. Correct setting of the MIFn_WORD_SIZE field ensures that each data word is transmitted/received as Most- Significant-Byte first. 00 = 8-bit (1, 2, 3, 4, 5, 6, 7, 8, etc) 01 = 16-bit (2, 1, 4, 3, 6, 5, 8, 7, etc) 10 = 32-bit (4, 3, 2, 1, 8, 7, 6, 5, etc) The numbers in brackets describe the order in which the applicable MIFn_[TX|RX]_BYTEx fields are transmitted/received over the I2C interface. 0 MIFn_READ_WRITE_SEL 0 Selects the I2C Command type 0 = Master Write 1 = Master Read base address +106h MIFn_CONFIG_4 20:0 MIFn_TX_LENGTH [20:0] 00_0000h Selects the total number of data bytes in an I2C Write operation. 00_0000h = 1 byte 00_0001h = 2 bytes 00_0002h = 3 bytes … 1F_FFFFh = 2,097,152 bytes |
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