CS47L85 datasheet(146/370 Pages) CIRRUS

146 / 370 page

CS47L85

146

Rev 4.3

EVENT LOGGERS

The CS47L85 provides 8 Event Log functions, supporting multi-channel, edge-sensitive monitoring and recording of internal

or external signals. An “event” is recorded when a logic transition (edge) is detected on a selected signal source. The Event

Loggers allow status information to be captured from a large number of sources, to be prioritised and acted upon as required.

The logged events are held in a FIFO buffer, which is managed by the application software. A 32-bit timestamp, derived

from one of the General Purpose Timers, is associated and recorded with each FIFO index, to provide a comprehensive

record of the detected events.

Each Event Logger must be associated with one of the General Purpose Timers. The selected Timer is the source of

timestamp data for any logged events. If DSPCLK is disabled, then the Timer also provides the clock source for the Event

Logger. (If DSPCLK is enabled, then DSPCLK is used as the clock source instead.)

A maximum of one event per cycle of the clock source (see above) can be logged. If more than one event occurs within the

cycle time, then the highest priority (lowest channel number) event will be logged at the rising edge of the clock. In this case,

any lower priority events will be queued, and will be logged as soon as no higher priority events are pending. It is possible

for recurring events on a high priority channel to be logged, while low priority ones remain queued. Note that recurring

instances of events that are ‘queued’ would not be logged.

The Event Logger can use a slow clock (e.g., 32kHz), but higher clock frequencies may also be commonly used, depending

on the application and use case. The clock frequency determines the maximum possible event logging rate, as described

above.

The Event Logger is enabled using the EVENTLOG

n_ENA register bit (where ‘n’ identifies the respective Event Logger, 1

to 8).

The Event Logger can be reset by writing ‘1’ to the EVENTLOGn_RST bit. Executing this function will clear all the Event

Logger status flags, and will clear the contents of the FIFO buffer.

The associated Timer (and timestamp source) is selected using EVENTLOGn_TIME_SEL. Note that the Event Logger must

be disabled (EVENTLOGn_ENA = 0) when selecting the Timer source.

The Event Logger allows up to 16 input channels to be configured for detection and logging. The EVENTLOGn_CHx_SEL

register selects the applicable input source for each channel (where ‘x’ identifies the channel number, 1 to 16). The polarity

selection and de-bounce options are configured using the EVENTLOGn_CHx_POL and EVENTLOGn_CHx_DB bits

respectively.

The input channels can be enabled or disabled freely, using EVENTLOGn_CHx_ENA, without having to disable the Event

Logger entirely. An input channel must be disabled whenever the associated _SEL, _POL, or _DB fields are written. It is

possible to re-configure input channels while the Event Logger is enabled, provided the channel(s) being re-configured are

disabled when doing so.

The available input sources include GPIO inputs, External Accessory status (Jack, Mic, Sensors), and signals generated by

the integrated DSP Cores. A list of the valid input sources for the Event Loggers is provided in Table 34.

Note that, to log both rising and falling events from any source, two separate input channels must be configured - one for

each polarity.

If an Input channel is configured for Rising Edge detection (EVENTLOGn_CHx_POL=0), and the corresponding input signal

is ‘Logic 1’ at the time when the Event Logger is enabled, then an event will be logged in respect of this initial state. Similarly,

if an Input channel is configured for Falling Edge detection, and is Logic ‘0’ when the Event Logger is enabled, then a

corresponding event will be logged. If Rising and Falling edges are both configured for detection, then an event will always

be logged in respect of the initial condition.

Each event (signal transition) which meets the criteria of an enabled channel will be written to the 16-stage FIFO buffer. The

buffer is filled cyclically, but does not overwrite unread data when full. An error condition occurs if the buffer fills up completely.

Note the “FIFO” behaviour is not enforced or fully implemented in the device hardware, but assumes that a compatible

software implementation is in place. New events are written to the buffer in a cyclic manner, but the data can be read out in

any order, if desired. The designed FIFO behaviour requires the software to update the Read Pointer (RPTR) in the intended

manner for smooth operation.

The entire contents of the 16-stage FIFO buffer can be accessed directly in the register map. Each FIFO index (y = 0 to 15)

comprises

the

EVENTLOGn_FIFOy_ID

(identifying

the

source

signal

the

associated

log

event),

the

EVENTLOGn_FIFOy_POL (the polarity of the respective event transition), and the EVENTLOGn_FIFOy_TIME field

(containing the 32-bit timestamp, from the associated Timer).

CS47L85 Datasheet(PDF) 146 Page - Cirrus Logic

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