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CS47L85 Datasheet(PDF) 147 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 147 Page - Cirrus Logic

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CS47L85
Rev 4.3
147
The FIFO buffer is managed using the EVENTLOGn_FIFO_WPTR and EVENTLOGn_FIFO_RPTR registers. The Write
Pointer (WPTR) field identifies the index location (0 to 15) in which the next event will be logged. The Read Pointer (RPTR)
field identifies the index location of the first set of unread data, if any exists. Both of these fields are initialised to 0 when the
Event Logger is reset.
If RPTR <> WPTR, then the buffer contains new data. The number of new events is equal to the difference between the two
pointer values (WPTR - RPTR, allowing for wrap-around beyond index 15). For example, if WPTR = 12 and RPTR = 8, this
means that there are 4 unread data sets in the buffer, at index locations 8, 9, 10, and 11.
After reading the new data from the buffer, the RPTR value should be incremented by the corresponding amount (e.g.,
increment by 4, in the example described above). Note that the RPTR value can either be incremented once for each read,
or can be incremented in larger steps after a ‘batch’ read.
If RPTR = WPTR, then the buffer is either empty (0 events) or full (16 events). In this case, the status bits described below
will confirm the current status of the buffer.
The EVENTLOGn_NOT_EMPTY bit indicates whether the FIFO buffer is empty. When this bit is set, it indicates one or more
new sets of data in the FIFO.
The EVENTLOGn_WMARK_STS bit indicates when the number of FIFO index locations available for new events reaches
a configurable threshold, known as the watermark level. The watermark level is held in the EVENTLOGn_WMARK register.
The EVENTLOGn_FULL bit indicates when the FIFO buffer is full. When this bit is set, it indicates that there are 16 sets of
new event data in the FIFO. Note that this does not mean that a buffer overflow condition has occurred; but further events
will not be logged or indicated until the buffer has been cleared.
Following
a ‘Buffer Full’ condition, the FIFO operation will resume as soon as the RPTR field has been updated to a new
value. Note that writing the same value to RPTR will not re-start the FIFO operation, even if the entire buffer contents have
been read. After all of the required data has been read from the buffer, the RPTR value should be set equal to the WPTR
value; note that an intermediate (different) value must always be written to the RPTR field in order to clear the ‘Buffer Full’
status and re-start the FIFO operation.
The Control Write Sequencer is automatically triggered whenever the NOT_EMPTY status of the Event Log buffer is
asserted.
A different control sequence may be configured for each of the Event Loggers. See “Control Write Sequencer” for
further details.
The Event Log status flags are inputs to the Interrupt control circuit and can be used to trigger an Interrupt event when the
respective FIFO condition (Full, Not Empty, or Watermark level) occurs -
see “Interrupts”.
The Event Log status can be output directly on a GPIO pin as an external indication of the Event Logger. Se
e “General
Purpose Input / Output
” to configure a GPIO pin for this function.
The Event Log NOT_EMPTY status can also be selected as a ‘Start’ trigger for DSP firmware execution. See “DSP Firmware
Control
” for further details.



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