CS47L85 datasheet(140/370 Pages) CIRRUS

140 / 370 page

CS47L85

140

Rev 4.3

DSP PERIPHERAL CONTROL

The CS47L85 incorporates a suite of DSP peripheral functions, which can be integrated together to support the sensor hub

capability. Three Master I2C Interfaces are provided, for external sensor connectivity. Configurable Event Log functions

provide multi-channel monitoring of internal and external signals. The General Purpose Timers provide time-stamp data for

the Event Logs, and support watchdog and other miscellaneous time-based functions. Maskable GPIO provides an efficient

mechanism for multiple DSPs to access the respective input and output signals.

The DSP peripherals are designed to provide a comprehensive sensor hub capability, operating with a high degree of

autonomy from the host processor.

MASTER INTERFACES

The CS47L85 incorporates three I2C Master Interfaces, offering a flexible capability for additional sensor / accessory input.

The Master Interfaces (MIF1, MIF2, MIF3) can support single-master I2C operation up to 1MHz. The Master Interfaces

support 7-bit and 10-bit Slave addressing modes.

The Master Interfaces are ideally suited for connection to external sensors such as accelerometers, gyroscopes and

magnetometers for motion sensing and navigation applications. Other example accessories include barometers, or ambient

light sensors, for environmental awareness. Flow control bits for the TX and RX data buffers enable easy integration with

external devices, and with internal DSP functions.

Clocking for the Master Interfaces is derived from DSPCLK, which must be enabled and present when using any of these

interfaces. Standard I2C bus rates can be supported for typical DSPCLK frequencies using the register settings described

in Table 31.

ADDRESS

CONDITION

VALUE

MIFn Base Address

—

0x0000_0006

MIFn Base Address + 0x040

—

0x0000_0000

MIFn Base Address + 0x042

10kHz I2C mode

0x01CC_01CC

100kHz I2C mode

0x002E_002E

400kHz I2C mode

0x000C_000C

1MHz I2C mode

0x0005_0005

Notes:

The ‘Base Address’ register for each Master Interface (MIFn) is noted in Table 32.

2. It is assumed that the DSPCLK frequency is one of the nominal (typical) frequencies specified in Table 105.

Table 31 Master Interface Clock Configuration

The Transmit (Master Write) and Receive (Master Read) actions are each supported by 16-byte data buffers, allowing I2C

transfers of up to 2,097,152 data bytes (2MB). The number of data bytes transmitted (or received) in each I2C operation is

selected using the MIFn_TX_LENGTH (or MIFn_RX_LENGTH) field respectively.

Data to be transmitted is managed using the TX data buffers; the application software must load data into the buffer registers

(MIFn_TX_BYTEx), and then write ‘1’ to the MIFn_TX_DONE bit to commit that data for transmission. The

MIFn_TX_REQUEST bit indicates when the buffer registers are ready for loading new data. Internal buffering of the TX data

enables uninterrupted I2C Writes. If new data is not ready for transmission, SCLK will halt until the buffer registers have

been filled.

Data received on the interface is managed using the RX data buffers; the MIFn_RX_REQUEST bit indicates when the buffer

registers conta

in new data. The application software must read the buffer registers (MIFn_RX_BYTEn), and then write ‘1’ to

the MIFn_RX_DONE bit to confirm the data has been read. Internal buffering of the RX data enables uninterrupted I2C

Reads. If the buffers are not ready to receive new data, SCLK will halt until the buffer registers have been read.

The Master Interface divides each I2C transaction into one or more data Blocks. The Block Length is configurable using the

MIFn_TX_BLOCK_LENGTH and MIFn_RX_BLOCK_LENGTH register fields. The Block Length is equal to the number of

bytes transmitted/received for each TX_DONE/RX_DONE action. The maximum Block Length is 16 bytes, corresponding

to the size of the TX and RX data buffers.

Note that the order in which the data bytes in the TX/RX buffers are transferred depends upon the selected

MIFn_WORD_SIZE setting. Correct setting of the word size ensures that each data word is transmitted/received as Most-

Significant-Byte first.

The Master Interface is configured for Read (RX) or Write (TX) operation using the MIFn_READ_WRITE_SEL bit. Each I2C

transfer is started by writing 1 to the MIFn_START bit. In the case of a Master Write, data must be committed to the TX data

buffers using the TX_DONE bit, to enable the transfer to proceed - note that the first block of transmit data can be committed

to the TX buffers before or after writing to the START bit for the respective transfer.

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