CS47L85 datasheet(139/370 Pages) CIRRUS

139 / 370 page

CS47L85

Rev 4.3

139

DSP DEBUG SUPPORT

General purpose ‘scratch’ registers are provided for each DSP. These have no assigned function, and can be used to assist

in algorithm development.

The JTAG interface provides test and debug access to the CS47L85

, as described in the “JTAG Interface” section. The

JTAG interface clock can be enabled independently for each DSP core, using the DSPn_DBG_CLK_ENA register bits.

When using the JTAG interface to access any DSP core, the respective DSPn_DBG_CLK_ENA and DSPn_CORE_ENA

bits must also be set.

BIT

LABEL

DEFAULT

DESCRIPTION

DSP1 Base Address = R1048064 (0FFE00h)

DSP2 Base Address = R1572352 (17FE00h)

DSP3 Base Address = R2096640 (1FFE00h)

DSP4 Base Address = R2620928 (27FE00h)

DSP5 Base Address = R3145216 (2FFE00h)

DSP6 Base Address = R3669504 (37FE00h)

DSP7 Base Address = R4193792 (3FFE00h)

base address

DSPn_Config_1

DSPn_DBG_CLK_ENA

DSPn Debug Clock Enable

0 = Disabled

1 = Enabled

base address +40h

DSPn_Scratch_1

31:16

DSPn_SCRATCH_1 [15:0]

0000h

DSPn Scratch Register 1

15:0

DSPn_SCRATCH_0 [15:0]

0000h

DSPn Scratch Register 0

base address +42h

DSPn_Scratch_2

31:16

DSPn_SCRATCH_3 [15:0]

0000h

DSPn Scratch Register 3

15:0

DSPn_SCRATCH_2 [15:0]

0000h

DSPn Scratch Register 2

Table 30 DSP Debug Support

VIRTUAL DSP REGISTERS

The DSP control registers, described throughout this section, are implemented for each DSP core. Each control register has

a unique location within the CS47L85 register map.

An additional set of DSP control registers is also defined, which can be used in firmware to access any of the DSPs; these

are known as ‘Virtual DSP’ or ‘DSP 0’ registers, and are defined at address R4096 (1000h) in the device register map. The

full register map listing is provided in a separate document -

see “Register Map” for further information.

Note that read/write access to the Virtual DSP registers is only possible via firmware running on the integrated DSP cores.

When DSP firmware accesses the virtual registers, then the registers will automatically be mapped onto the control registers

corresponding to whichever DSP core is making the read/write access. For example, if DSP1 accesses these registers, then

the registers will read/write the DSP1 control registers. If DSP2 accesses the virtual registers, they will be mapped onto the

DSP2 control registers.

The Virtual DSP registers are designed to allow software to be transferable to any of the DSPs without modification to the

software code.

The Virtual DSP registers are defined at register addresses R4096 (1000h) to R4192 (1060h) in the device register map.

Note that these registers cannot be accessed directly at the addresses shown; they can only be accessed through DSP

firmware code, using the register window function illustrated in Figure 40. The virtual DSP registers are located at address

0xD000 in the X Data memory map.

CS47L85 Datasheet(PDF) 139 Page - Cirrus Logic

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