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CS47L85 Datasheet(PDF) 135 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 135 Page - Cirrus Logic |
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135 / 370 page ![]() CS47L85 Rev 4.3 135 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 23:16 DSPn_WDMA_ACTIVE_CH ANNELS [7:0] 00h DSPn WDMA Channel Status There are 8 WDMA channels; each bit of this field indicates the status of the respective WDMA channel. Each bit is coded as: 0 = Inactive 1 = Active base address +10h DSPn_WDMA_Buffer_1 31:16 DSPn_START_ADDRESS_ WDMA_BUFFER_1 [15:0] 0000h DSPn WDMA Channel 1 Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24- bit DSP memory word. Note that the start address is also controlled by the respective DSPn_WDMA_CHANNEL_OFFSET bit. 15:0 DSPn_START_ADDRESS_ WDMA_BUFFER_0 [15:0] 0000h DSPn WDMA Channel 0 Start Address Register description is as above. base address +12h DSPn_WDMA_Buffer_2 31:16 DSPn_START_ADDRESS_ WDMA_BUFFER_3 [15:0] 0000h DSPn WDMA Channel 3 Start Address Register description is as above. 15:0 DSPn_START_ADDRESS_ WDMA_BUFFER_2 [15:0] 0000h DSPn WDMA Channel 2 Start Address Register description is as above. base address +14h DSPn_WDMA_Buffer_3 31:16 DSPn_START_ADDRESS_ WDMA_BUFFER_5 [15:0] 0000h DSPn WDMA Channel 5 Start Address Register description is as above. 15:0 DSPn_START_ADDRESS_ WDMA_BUFFER_4 [15:0] 0000h DSPn WDMA Channel 4 Start Address Register description is as above. base address +16h DSPn_WDMA_Buffer_4 31:16 DSPn_START_ADDRESS_ WDMA_BUFFER_7 [15:0] 0000h DSPn WDMA Channel 7 Start Address Register description is as above. 15:0 DSPn_START_ADDRESS_ WDMA_BUFFER_6 [15:0] 0000h DSPn WDMA Channel 6 Start Address Register description is as above. base address +20h DSPn_RDMA_Buffer_1 31:16 DSPn_START_ADDRESS_ RDMA_BUFFER_1 [15:0] 0000h DSPn RDMA Channel 1 Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24- bit DSP memory word. Note that the start address is also controlled by the respective DSPn_RDMA_CHANNEL_OFFSET bit. |
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