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CS47L85 Datasheet(PDF) 132 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 132 Page - Cirrus Logic |
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132 / 370 page ![]() CS47L85 132 Rev 4.3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION DSP1 Base Address = R1048064 (0FFE00h) DSP2 Base Address = R1572352 (17FE00h) DSP3 Base Address = R2096640 (1FFE00h) DSP4 Base Address = R2620928 (27FE00h) DSP5 Base Address = R3145216 (2FFE00h) DSP6 Base Address = R3669504 (37FE00h) DSP7 Base Address = R4193792 (3FFE00h) base address DSPn_Config_1 18:16 DSPn_CLK_SEL [2:0] 000 DSPn Clock Frequency Select 000=5.5MHz to 9.375MHz 001=9.375MHz to 18.75MHz 010=18.75MHz to 37.5MHz 011=37.5MHz to 75MHz 100=75MHz to 150MHz All other codes are Reserved [DSP6, DSP7] – valid codes are 000 to 011 only. Note that, because DSPCLK could be any frequency (within the valid ranges), it is not possible to quote exact frequencies in this register definition. The DSPn Clock must be less than or equal to the DSPCLK frequency. The exact frequency will be derived as DSPCLK divided by 1, 2, 4, 8, or 16. 4 DSPn_MEM_ENA 0 DSPn Memory Control 0 = Disabled 1 = Enabled The DSPn memory contents are lost when DSPn_MEM_ENA=0. Note that this bit is not affected by Software Reset; it will remain in its previous condition. [DSP6 only] – This bit has no function; DSP6 memory is enabled at all times. 1 DSPn_CORE_ENA 0 DSPn Enable Controls the DSPn firmware execution 0 = Disabled 1 = Enabled 0 DSPn_START DSPn Start Write ‘1’ to Start DSPn firmware execution base address +06h DSPn_Status_2 31:16 DSPn_DUALMEM_COLLISI ON_ADDR [15:0] 0000h DSPn Dual Memory Collision Address In the event of a DSPn memory access collision, this field will report the address at which the collision occurred. The address is defined relative to the base address of the shared data memory. The LSB represents one 24- bit DSP memory word. |
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