CS47L85 datasheet(128/370 Pages) CIRRUS

128 / 370 page

CS47L85

128

Rev 4.3

DESCRIPTION

DSP MEMORY SIZE

DSP1

Program memory

08_0000h to 08_5FFEh

(12288 registers)

8k x 40-bit words

X Data memory

0A_0000h to 0A_7FFEh

(16384 registers)

16k x 24-bit words

Y Data memory

0C_0000h to 0C_1FFEh

(4096 registers)

4k x 24-bit words

Coefficient memory

0E_0000h to 0E_1FFEh

(4096 registers)

4k x 24-bit words

DSP2

Program memory

10_0000h to 10_EFFEh

(30720 registers)

20k x 40-bit words

X Data memory

12_0000h to 12_BFFEh

(24576 registers)

24k x 24-bit words

X Data memory

(Shared DSP2/DSP3)

13_6000h to 13_7FFEh

(4096 registers)

4k x 24-bit words

Y Data memory

14_0000h to 14_BFFEh

(24576 registers)

24k x 24-bit words

Coefficient memory

16_0000h to 16_1FFEh

(4096 registers)

4k x 24-bit words

DSP3

Program memory

18_0000h to 18_EFFEh

(30720 registers)

20k x 40-bit words

X Data memory

1A_0000h to 1B_1FFEh

(36864 registers)

36k x 24-bit words

X Data memory

(Shared DSP2/DSP3)

1B_6000h to 1B_7FFEh

(4096 registers)

4k x 24-bit words

Y Data memory

1C_0000h to 1C_BFFEh

(24576 registers)

24k x 24-bit words

Coefficient memory

1E_0000h to 1E_1FFEh

(4096 registers)

4k x 24-bit words

DSP4

Program memory

20_0000h to 20_8FFEh

(18432 registers)

12k x 40-bit words

X Data memory

22_0000h to 23_1FFEh

(36864 registers)

36k x 24-bit words

Y Data memory

24_0000h to 24_BFFEh

(24576 registers)

24k x 24-bit words

Coefficient memory

26_0000h to 26_1FFEh

(4096 registers)

4k x 24-bit words

DSP5

Program memory

28_0000h to 28_8FFEh

(18432 registers)

12k x 40-bit words

X Data memory

2A_0000h to 2A_9FFEh

(20480 registers)

20k x 24-bit words

Y Data memory

2C_0000h to 2C_3FFEh

(8192 registers)

8k x 24-bit words

Coefficient memory

2E_0000h to 2E_1FFEh

(4096 registers)

4k x 24-bit words

DSP6

Program memory

30_0000h to 30_5FFEh

(12288 registers)

8k x 40-bit words

X Data memory

32_0000h to 33_3FFEh

(40960 registers)

40k x 24-bit words

Y Data memory

34_0000h to 34_BFFEh

(24576 registers)

24k x 24-bit words

Coefficient memory

36_0000h to 36_1FFEh

(4096 registers)

4k x 24-bit words

DSP7

Program memory

38_0000h to 38_8FFEh

(18432 registers)

12k x 40-bit words

X Data memory

3A_0000h to 3A_7FFEh

(16384 registers)

16k x 24-bit words

Y Data memory

3C_0000h to 3C_1FFEh

(4096 registers)

4k x 24-bit words

Coefficient memory

3E_0000h to 3E_1FFEh

(4096 registers)

4k x 24-bit words

Table 25 DSP Program, Coefficient and Data Registers

The X-Memory on each DSP supports read/write access to all register fields throughout the device - including the CODEC

control registers, and the firmware memory of all of the integrated DSP cores. Access to the register address space is

supported using a number of register ‘windows’ within the X-Memory on each DSP.

The register window space is additional to the X Data memory sizes described in Table 25. Note that the X-memory

addresses of these register windows are the same for all DSP cores - regardless of the different X-memory sizes.

Addresses 0xC000 to 0xDFFF in X-Memory map directly to addresses 0x0000 to 0x1FFF in the device register space. This

fixed register window contains primarily the CODEC control registers; it also includes the ‘Virtual DSP’ control registers

(described later in this section). Each X-Memory address within this window maps onto one 16-bit register in the CODEC

memory space.

Four moveable register windows are also provided, starting at X-Memory addresses 0xF000, 0xF400, 0xF800, and 0xFC00

respectively. Each window represents 1024 addresses in the X-Memory space. The start address, within the corresponding

device register space, for each window is configured using the DSPn_EXT_[A/B/C/D]_PAGE registers (where ‘A’ defines

the first window, ‘B’ defines the second window, etc.).

Two different mapping modes are supported, selected using the DSPn_EXT_[A/B/C/D]_PSIZE16 control bits for the

respective window. In 16-bit mode, each address within the window maps onto one 16-bit register in the device memory

space; the window equates to 1024 x 16-bit registers. In 32-bit mode, each address within the window maps onto two 16-bit

registers in the device memory space; the window equates to 1024 x 32-bit registers.

Note that the X-Memory is only 24-bits wide; as a result, the upper 8 bits of the odd-numbered register addresses are not

mapped, and cannot be accessed, in 32-bit mode.

The DSPn_EXT_[A/B/C/D]_PAGE registers are defined with an LSB = 512. Accordingly, the base address of each window

CS47L85 Datasheet(PDF) 128 Page - Cirrus Logic

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