CS47L85 datasheet(134/370 Pages) CIRRUS

134 / 370 page

CS47L85

134

Rev 4.3

DSP DIRECT MEMORY ACCESS (DMA) CONTROL

Each DSP provides a multi-channel DMA function; this is configured using the registers described in Table 28.

There are 8 WDMA (DSP input) and 6 RDMA (DSP output) channels for each DSP; these are enabled using the

DSPn_WDMA_CHANNEL_ENABLE and DSPn_RDMA_CHANNEL_ENABLE fields. The status of each WDMA channel is

indicated in DSPn_WDMA_ACTIVE_CHANNELS.

The DMA can access the X data memory or Y data memory associated with the respective DSP. The applicable memory is

selected using bit [15] of the respective *_START_ADDRESS register.

The start address of each DMA channel is configured as described in Table 28. Note that the required address is defined

relative to the base address of the selected (X data or Y data) memory.

The buffer length of the DMA channels is configured using the DSPn_DMA_BUFFER_LENGTH field. The selected buffer

length applies to all enabled DMA channels.

Note that the start address registers, and buffer length registers, are defined in 24-bit DSP data word units. This means that

the LSB of these fields represents one 24-bit DSP memory word. (Note that this differs from the CS47L85 register map

layout, as described in Table 25).

The parameters of a DMA channel (i.e., Start Address or Offset Address) must not be changed whilst the respective DMA

is enabled. All of the DMA channels must be disabled before changing the DMA buffer length.

Each DMA channel uses a twin buffer mechanism to support uninterrupted data flow through the DSP. The buffers are called

‘ping’ and ‘pong’ respectively, and are of configurable size, as noted above. Data is transferred to/from each of the buffers

in turn.

When the ‘ping’ input data buffer is full, the DSPn_PING_FULL bit will be asserted (set to ‘1’), and a ‘DSP Start’ signal will

be generated

. The ‘Start’ signal from the DMA is typically used to start Firmware execution, as noted in Table 27. Meanwhile,

further DSP input data will be filling up the ‘pong’ buffer.

When the ‘pong’ input buffer is full, the DSPn_PONG_FULL bit will be asserted, and another ‘DSP Start’ signal will be

generated. The DSP Firmware must take care to read the input data from the applicable buffer, in accordance with the

DSPn_PING_FULL and DSPn_PONG_FULL status bits.

Twin buffers are also used on the DSP output (RDMA) channels. The output ‘ping’ buffers are emptied at the same time as

the input ‘ping’ buffers are filled; the output ‘pong’ buffers are emptied at the same time as the input ‘pong’ buffers are filled.

The DSP cores support 24-

bit signal processing. Under default conditions, the DSP audio data is in 2’s complement Q3.20

format (ie. 0xF00000 corresponds to the -1.0 level, and 0x100000 corresponds to the +1.0 level; a sine wave with peak

values of +/-1.0 corresponds to the 0 dBFS level). If DSPn_DMA_WORD_SEL is set, audio data is transferred to and from

DSPn in Q0.23 format. The applicable format should be set according to the requirements of the specific DSP firmware.

Note that the DSP cores are optimised for Q3.20 audio data processing; Q0.23 data can be supported, but the firmware

implementation may incur a reduction in power efficiency due to the higher MIPS required for arithmetic operations in non-

native data word format.

The DSPCLK system clock must be configured and enabled before any DMA channel is enabled. The DMA channels should

be kept disabled (DSPn_[WDMA/RDMA]_CHANNEL_ENABLE=00h

) if DSPCLK is not enabled. See “Clocking and Sample

Rates

” for details of the system clocks (including requirements for reconfiguring DSPCLK while DMA channels are enabled).

Further details of the DMA are provided in the software programming guide - please contact your local Cirrus Logic

representative if required.

BIT

LABEL

DEFAULT

DESCRIPTION

DSP1 Base Address = R1048064 (0FFE00h)

DSP2 Base Address = R1572352 (17FE00h)

DSP3 Base Address = R2096640 (1FFE00h)

DSP4 Base Address = R2620928 (27FE00h)

DSP5 Base Address = R3145216 (2FFE00h)

DSP6 Base Address = R3669504 (37FE00h)

DSP7 Base Address = R4193792 (3FFE00h)

base address +04h

DSPn_Status_1

DSPn_PING_FULL

DSPn WDMA Ping Buffer Status

0 = Not Full

1 = Full

DSPn_PONG_FULL

DSPn WDMA Pong Buffer Status

0 = Not Full

1 = Full

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