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CS47L85 Datasheet(PDF) 123 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 123 Page - Cirrus Logic

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CS47L85
Rev 4.3
123
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
13
ISRC1_INT3_EN
A
0
ISRC1 INT3 Enable
(Interpolation Channel 3 path from
ISRC1_FSL rate to ISRC1_FSH rate)
0 = Disabled
1 = Enabled
12
ISRC1_INT4_EN
A
0
ISRC1 INT4 Enable
(Interpolation Channel 4 path from
ISRC1_FSL rate to ISRC1_FSH rate)
0 = Disabled
1 = Enabled
9
ISRC1_DEC1_EN
A
0
ISRC1 DEC1 Enable
(Decimation Channel 1 path from
ISRC1_FSH rate to ISRC1_FSL rate)
0 = Disabled
1 = Enabled
8
ISRC1_DEC2_EN
A
0
ISRC1 DEC2 Enable
(Decimation Channel 2 path from
ISRC1_FSH rate to ISRC1_FSL rate)
0 = Disabled
1 = Enabled
7
ISRC1_DEC3_EN
A
0
ISRC1 DEC3 Enable
(Decimation Channel 3 path from
ISRC1_FSH rate to ISRC1_FSL rate)
0 = Disabled
1 = Enabled
6
ISRC1_DEC4_EN
A
0
ISRC1 DEC4 Enable
(Decimation Channel 4 path from
ISRC1_FSH rate to ISRC1_FSL rate)
0 = Disabled
1 = Enabled
R3827
(0EF3h)
ISRC2_CT
RL_1
14:11
ISRC2_FSH [3:0]
0000
ISRC2 High Sample Rate
(Sets the higher of the ISRC2 sample
rates)
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
1000 = ASYNC_SAMPLE_RATE_1
1001 = ASYNC_SAMPLE_RATE_2
All other codes are Reserved.
The selected sample rate is valid in the
range 8kHz to 192kHz.
The ISRC2_FSH and ISRC2_FSL fields
must both select sample rates referenced
to the same clock domain (SYSCLK or
ASYNCCLK).
All ISRC2_DECn_SRC registers should
be set to 00h before changing
ISRC2_FSH.



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