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CS47L85 Datasheet(PDF) 220 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 220 Page - Cirrus Logic |
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220 / 370 page  CS47L85 220 Rev 4.3 OUTPUT SIGNAL PATH AEC LOOPBACK The CS47L85 incorporates two loopback signal paths, which are ideally suited as a reference for Acoustic Echo Cancellation (AEC) processing. Any two of the output signal paths may be selected as the AEC loopback sources. When configured with suitable DSP firmware, the CS47L85 can provide an integrated AEC capability. The AEC loopback feature also enables convenient hook-up to an external device for implementing the required signal processing algorithms. The AEC Loopback source is connected after the respective digital volume controls, as illustrated in Figure 60. The AEC Loopback signals can be selected as input to any of the digital mixers within the CS47L85 digital core. The sample rate for the AEC Loopback paths is configured using the OUT_RATE register - see Table 22 within the “Digital Core” section. The AEC loopback function is enabled using the AECn _LOOPBACK_ENA register bits, (where ‘n’ identifies the applicable path, AEC1 or AEC2). The source signals for the Transmit Path AEC function are selected using the AECn_LOOPBACK_SRC bits. The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the AEC Loopback function. If an attempt is made to enable this function, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The AECn_ENA_STS register bits indicate the status of the AEC Loopback functions. If an Underclocked Error condition occurs, then these bits can provide indication of whether the AEC Loopback function has been successfully enabled. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1104 (0450h) DAC_AEC _Control_ 1 5:2 AEC1_LOOPBAC K_SRC [3:0] 0000 Input source for Tx AEC1 function 0000 = OUT1L 0001 = OUT1R 0010 = OUT2L 0011 = OUT2R 0100 = OUT3 0110 = OUT4L 0111 = OUT4R 1000 = OUT5L 1001 = OUT5R 1010 = OUT6L 1011 = OUT6R All other codes are Reserved 1 AEC1_ENA_STS 0 Transmit (Tx) Path AEC1 Control Status 0 = Disabled 1 = Enabled 0 AEC1_LOOPBAC K_ENA 0 Transmit (Tx) Path AEC1 Control 0 = Disabled 1 = Enabled R1105 (0451h) DAC_AEC _Control_ 2 5:2 AEC2_LOOPBAC K_SRC [3:0] 0000 Input source for Tx AEC2 function 0000 = OUT1L 0001 = OUT1R 0010 = OUT2L 0011 = OUT2R 0100 = OUT3 0110 = OUT4L 0111 = OUT4R 1000 = OUT5L 1001 = OUT5R 1010 = OUT6L 1011 = OUT6R All other codes are Reserved 1 AEC2_ENA_STS 0 Transmit (Tx) Path AEC2 Control Status 0 = Disabled 1 = Enabled 0 AEC2_LOOPBAC K_ENA 0 Transmit (Tx) Path AEC2 Control 0 = Disabled 1 = Enabled Table 79 Output Signal Path AEC Loopback Control |
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