CS47L85 datasheet(224/370 Pages) CIRRUS

224 / 370 page

CS47L85

224

Rev 4.3

SPEAKER OUTPUTS (DIGITAL PDM)

The CS47L85 supports a four-channel Pulse Density Modulation (PDM) digital speaker interface; the PDM outputs are

associated with the OUT5L, OUT5R, OUT6L and OUT6R output signal paths.

The PDM digital speaker interface comprises two stereo interfaces; the operation of one interface is illustrated in Figure 64.

The external connections associated with the PDM outputs are implemented on multi-function GPIO pins, which must be

configured for the respective PDM functions when required. The PDM output connections are pin-specific alternative

functions available on specific GPIO pins. See “General Purpose Input / Output” to configure the GPIO pins for the PDM

output.

The OUT5L and OUT5R output signal paths are interleaved on the SPKDAT1 output, and clocked using SPKCLK1. The

OUT6L and OUT6R output signal paths are interleaved on the SPKDAT2 output, and clocked using SPKCLK2.

Note that the PDM interface supports two different operating modes; these are selected using the SPK1_FMT and

SPK2_FMT register bits. See “Signal Timing Requirements” for detailed timing information in both modes.

When SPKn_FMT = 0 (Mode A), then the Left PDM channel is valid at the rising edge of SPKCLK; the Right PDM channel

is valid at the falling edge of SPKCLK.

When SPKn_FMT = 1 (Mode B), then the Left PDM channel is valid during the low phase of SPKCLK; the Right PDM

channel is valid during the high phase of SPKCLK.

SPKCLK output (Mode A)

SPKDAT output

(left & right channels interleaved)

Left channel output

Right channel output

SPKCLK output (Mode B)

Figure 64 Digital Speaker (PDM) Interface Timing

Clocking for the PDM interface is derived from SYSCLK. Note that the SYSCLK_ENA register must also be set. See

“Clocking and Sample Rates” for further details of the system clocks and control registers.

When the OUT5L or OUT5R output signal path is enabled, the PDM interface clock signal is output on the SPKCLK1 pin.

When the OUT6L or OUT6R output signal path is enabled, the PDM interface clock signal is output on the SPKCLK2 pin.

The output signal paths support normal and high performa

nce operating modes, as described in the “Output Signal Path”

section. The SPKCLKn frequency is set according to the operating mode of the relevant output path, as described in Table

82. The OUT5_OSR and OUT6_OSR register bits are defined in Table 73.

Note that the SPKCLKn frequencies noted in Table 82 and Table 83 assume that the SYSCLK frequency is a multiple of

6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz (SYSCLK_FRAC=1), then the

SPKCLKn frequencies will be scaled accordingly.

OUT5_OSR

DESCRIPTION

SPKCLK1 FREQUENCY

Normal mode

3.072MHz

High Performance mode

6.144MHz

Table 82 SPKCLK1 Frequency

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