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CS47L85 Datasheet(PDF) 227 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 227 Page - Cirrus Logic

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CS47L85
Rev 4.3
227
EXTERNAL ACCESSORY DETECTION
The CS47L85 provides external accessory detection functions which can sense the presence and impedance of external
components. This can be used to detect the insertion or removal of an external headphone or headset, and to provide an
indication of key/button push events.
Jack insertion is detected using the JACKDET1 and JACKDET2 pins, which must be connected to a switch contact within
the jack socket(s). An Interrupt event is generated whenever a jack insertion or jack removal event is detected.
Suppression of pops and clicks caused by jack insertion or removal is provided using the MICDET clamp function. This
function can also be used to trigger interrupt events, and/or to trigger the Control Write Sequencer. The integrated General
Purpose Switch can be synchronised with the MICDET clamp, to provide additional pop suppression capability.
Microphones, push-buttons and other accessories can be detected via the MICDET1 or MICDET2 pins. The presence of a
microphone, and the status of a hookswitch can be detected. This feature can also be used to detect push-button operation.
Headphone impedance can be detected via the HPDETL and HPDETR pins; this can be used to set different gain levels or
other configuration settings according to the type of load connected. For example, different settings may be applicable to
Headphone or Line output loads.
The MICVDD power domain must be enabled when using the Microphone Detect function. (Note that MICVDD is not required
for the Jack Detect or Headphone Detect functions.) The MICVDD power domain is provided using an internal Charge Pump
(CP2) and LDO Regulator (LDO2). See “Charge Pumps, Regulators and Voltage Reference” for details of these circuits.
The internal 32kHz clock must be present and enabled when using the Microphone Detect or Headphone Detect functions;
the 32kHz clock is also required for the Jack Detect function, assuming input de-
bounce is enabled. See “Clocking and
Sample Rates
” for details of the internal 32kHz clock and associated register control fields.
JACK DETECT
The CS47L85 provides support for jack insertion switch detection. The jack insertion status can be read using the relevant
register status bits. A jack insertion or removal can also be used to trigger an interrupt (IRQ) event.
The jack detect interrupt (IRQ) functionality is maintained in Sleep mode (see “Low Power Sleep Configuration”). This
enables a jack insertion event to be used to trigger a Wake-Up of the CS47L85.
Jack insertion and removal is detected using the JACKDET1 and JACKDET2 pins. The recommended external connections
are illustrated in Figure 66. The logic thresholds a
ssociated with the JACKDETn pins are the same, as noted in the “Electrical
Characteristics
” section. Note that an external resistor (e.g., 500k
) connected to JACKDET2 is recommended, in order to
reduce leakage current.
The jack detect feature is enabled using the JDn_ENA register bits (where n = 1 or 2 for JACKDET1 or JACKDET2
respectively); the jack insertion status can be read using the JDn_STSx register bits.
The jack detect input de-bounce is selected using the JDn_DB register bits, as described in Table 85. Note that, under
normal operating conditions, the de-bounce circuit uses the 32kHz clock, which must be enabled whenever input de-bounce
functions are required. Input de-bounce is not provided in Sleep mode; the JDn_DB register bits have no effect in Sleep
mode.
Note that the Jack Detect signals, JD1 and JD2, can be used as inputs to the MICDET Clamp function. This provides
additional functionality relating to jack insertion or jack removal events.
An Interrupt Request (IRQ) event is generated whenever a jack insertion or jack removal is detected (see “Interrupts”).
Separate ‘mask’ bits are provided, to allow IRQ events on the rising and/or falling edges of the JD1 or JD2 signals.
The control registers associated with the Jack Detect function are described in Table 85.



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