CS47L85 datasheet(229/370 Pages) CIRRUS

229 / 370 page

CS47L85

Rev 4.3

229

The threshold voltages for the jack detect circuit are noted in the “Electrical Characteristics”. Note that separate thresholds

are defined for jack insertion and jack removal.

JACKDETn

reference

AVDD

Jack Detect logic



(jack insertion switch)

Note: The illustrated circuit assumes the

jack insertion switch contacts are closed

when jack is inserted.

Figure 67 Jack Detect Comparator

JACK POP SUPPRESSION (MICDET CLAMP AND GP SWITCH)

Under typical configuration of a 3.5mm headphone/accessory jack connection, there is a risk of pops and clicks arising from

jack insertion or removal. This can occur when the headphone load makes momentary contact with the MICBIAS output

when the jack is not fully inserted, as illustrated in Figure 68.

The CS47L85 provides a MICDET Clamp function to suppress pops and clicks caused by jack insertion or removal. The

clamp can be controlled directly, or can be activated by a configurable logic function derived from external logic inputs. The

clamp status can be read using the relevant register status bit. The clamp status can also be used to trigger an interrupt

(IRQ) event or to trigger the Control Write Sequencer.

The MICDET Clamp function can be configured using the MICD_CLAMP_MODE register field; the selectable logic

conditions (derived from the JD1 and/or JD2 signals - see Table 85) provide support for different jack detect circuit

configurations. The MICD_CLAMP_OVD bit, when set, will activate the MICDET Clamp, regardless of other conditions.

Note that the MICD_CLAMP_OVD bit is enabled by default; the MICDET Clamp is always active following Power-On Reset

(POR), Hardware Reset, or Software Reset.

The MICDET Clamp functionality (including the external IRQ) is maintained in Sleep mode (see “Low Power Sleep

Configuration

”). This enables a jack insertion event to be used to trigger a Wake-Up of the CS47L85.

A summary of the Jack Detect and MICDET Clamp functionality, and their recommended usage in typical applications, is

described in the next section.

When the MICDET Clamp is active, the MICDET1/HPOUT1FB2 and HPOUT1FB1/MICDET2 pins are short-circuited

together. The grounding of the MICDET pin is achieved via the applicable HPOUT1FB pin; note that it is assumed that the

HPOUT1FB connection is grounded externally, as shown in Figure 68.

The configurable logic provides flexibility in selecting the appropriate conditions for activating the MICDET Clamp. The clamp

status can be read using the MICD_CLAMP_STS register.

The MICDET Clamp de-bounce is selected using the MICD_CLAMP_DB register, as described in Table 86. Note that, under

normal operating conditions, the de-bounce circuit uses the 32kHz clock, which must be enabled whenever input de-bounce

functions are required. Input de-bounce is not provided in Sleep mode; the MICD_CLAMP_DB register bit has no effect in

Sleep mode.

An Interrupt Request (IRQ) event is generated whenever the MICDET Clamp is asserted or de-

asserted (see “Interrupts”).

Separate ‘mask’ bits are provided to enable IRQ events on the rising and/or falling edge of the MICDET Clamp status.

The Control Write Sequencer can be triggered by the MICDET Clamp status. This is enabled using the

WSEQ_ENA_MICD_CLAMP_FALL and WSEQ_ENA_MICD_CLAMP_RISE register bits.

See “Control Write Sequencer”

for further details.

The MICDET Clamp function is illustrated in Figure 68. Note that the jack plug is shown partially removed, with the MICDET1

pin in contact with the headphone load.

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