CS47L85 datasheet(257/370 Pages) CIRRUS

257 / 370 page

CS47L85

Rev 4.3

257

INTERRUPTS

The Interrupt Controller has multiple inputs. These include the Jack Detect and GPIO input pins, DSP_IRQn flags,

headphone / accessory detection, FLL / ASRC Lock detection, and status flags from DSP peripheral functions. (See Table

100 and Table 101 for a full definition of the Interrupt Controller inputs.) Any combination of these inputs can be used to

trigger an Interrupt Request (IRQ) event.

The Interrupt Controller supports two sets of interrupt registers. This allows two separate Interrupt Request (IRQ) outputs to

be generated, and for each IRQ to report a different set of input or status conditions.

For each Interrupt Request (IRQ1 and IRQ2) output, there is an Interrupt register field associated with each of the interrupt

inputs. These fields are asserted whenever a logic edge is detected on the respective input. Some inputs are triggered on

rising edges only; some are triggered on both edges. Separate rising and falling interrupt registers are provided for the JD1

and JD2 signals. The Interrupt register fields for IRQ1 are described in Table 100. The Interrupt register fields for IRQ2 are

described in Table 101. The Interrupt flags can be polled at any time, or else in response to the Interrupt Request (IRQ)

output being signalled via the IRQ

¯¯¯ pin or a GPIO pin.

All of the Interrupts are edge-triggered, as noted above. Many of these are triggered on both the rising and falling edges

and, therefore, the Interrupt registers cannot indicate which edge has been detected. The “Raw Status” fields described in

Table 100 and Table 101 provide readback of the current value of the corresponding inputs to the Interrupt Controller. Note

that the “Raw Status” bits associated with IRQ1 and IRQ2 both provide the same readback information. The status of any

GPIO (or DSP GPIO) inputs can also be read using the GPIO (or DSP GPIO) control registers, as described in Table 94

and Table 36.

Individual mask bits can enable or disable different functions from the Interrupt controller. The mask bits are described in

Table 100 (for IRQ1) and Table 101 (for IRQ2). Note that a masked interrupt input will not assert the corresponding interrupt

The Interrupt Request (IRQ) outpu

ts represent the logical ‘OR’ of the associated interrupt registers. (IRQ1 is derived from

the _EINT1 registers; IRQ2 is derived from the _EINT2 registers). The Interrupt register fields are latching fields and, once

they are set, they are not reset until

a ‘1’ is written to the respective register bit(s). The Interrupt Request (IRQ) outputs are

not reset until each of the associated interrupts has been reset.

A de-bounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin using the

GPIO de-bounce function is required.

A de-bounce circuit is always enabled on the FLL status inputs; either the 32kHz clock, or the SYSCLK signal, must be

enabled to trigger an I

nterrupt from the FLL status inputs. Note that the “Raw Status” fields (described in Table 100 and

Table 101), are valid without clocking, and can be used to provide FLL status readback when system clocks are not available.

The IRQ outputs can be globally masked using the IM_IRQ1 and IM_IRQ2 register bits. When not masked, the IRQ status

can be read from IRQ1_STS and IRQ2_STS for the respective IRQ outputs.

The IRQ1 output is provided externally on the IRQ

¯¯¯

pin. Under default conditions, this output is ‘Active Low’. The polarity can

be inverted using the IRQ_POL register. The IRQ

¯¯¯ output can be either CMOS driven or Open Drain; this is selected using

the IRQ_OP_CFG register. Note that the IRQ

¯¯¯ output is referenced to the DBVDD1 power domain.

The IRQ2 status can be used to trigger DSP firmware execution -

see “DSP Firmware Control”. This allows the DSP firmware

execution to be linked to external events (e.g., Jack detection, or GPIO input), or to any of the status conditions flagged by

the Interrupt registers.

The IRQ1 and IRQ2 signals may be output on a GPIO pin -

see “General Purpose Input / Output”.

The CS47L85 Interrupt Controller circuit is illustrated in Figure 73. (Note that not all interrupt inputs are shown.) The control

fields associated with IRQ1 and IRQ2 are described in Table 100 and Table 101 respectively. The global interrupt mask bits,

status bits, and output configuration register are described in Table 102.

Note that, under default register conditions, the ‘Boot Done’ status is the only un-masked interrupt source; a falling edge on

the IRQ

¯¯¯ pin will indicate completion of the Boot Sequence.

CS47L85 Datasheet(PDF) 257 Page - Cirrus Logic

CS47L85 Datasheet(HTML) 257 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL