CS47L85 datasheet(253/370 Pages) CIRRUS

253 / 370 page

CS47L85

Rev 4.3

253

FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT

GPn_FN = 018h, 019h, 01Ah.

The CS47L85 supports FLL status flags, which may be used to control other events.

The ‘FLL Lock’ signals indicate whether

FLL Lock has been achieved.

See “Clocking and Sample Rates” for more details of the FLL.

The FLL Lock signals may be output directly on a

GPIO pin by setting the respective GPIO registers as described in “GPIO

Control

”.

The FLL Lock signals are inputs to the Interrupt Controller circuit. An interrupt event is triggered on the rising and falling

edges of these signals. The associated interrupt bits are latched once set; they can be polled at any time or used to control

the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

OPCLK AND OPCLK_ASYNC CLOCK OUTPUT

GPn_FN = 040h, 041h.

A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. The OPCLK frequency is controlled by

OPCLK_DIV and OPCLK_SEL. The OPCLK output is enabled using the OPCLK_ENA register, as described in Table 98.

A clock output (OPCLK_ASYNC) derived from ASYNCCLK can be output on a GPIO pin. The OPCLK_ASYNC frequency

is controlled by OPCLK_ASYNC_DIV and OPCLK_ASYNC_SEL. The OPCLK_ASYNC output is enabled using the

OPCLK_ASYNC_ENA register

It is recommended to disable the clock output (OPCLK_ENA=0 or OPCLK_ASYNC_ENA=0) before making any change to

the respective OPCLK_DIV, OPCLK_SEL, OPCLK_ASYNC_DIV or OPCLK_ASYNC_SEL registers.

The OPCLK output should be kept disabled (OPCLK_ENA=0) if SYSCLK is not enabled. SYSCLK must be present and

enabled before setting the OPCLK_ENA bit. See “Clocking and Sample Rates” for further details (including requirements

for reconfiguring SYSCLK while digital core functions are enabled).

The OPCLK or OPCLK_ASYNC Clock outputs can be output directly on a GPIO pin by setting the respective GPIO registers

as described in “GPIO Control”.

Note that the OPCLK source frequency cannot be higher than the SYSCLK frequency. The OPCLK_ASYNC source

frequency cannot be higher than the ASYNCCLK frequency. The maximum output frequency supported for GPIO output is

noted in the “Electrical Characteristics”.

ee “Clocking and Sample Rates” for more details of the system clocks (SYSCLK and ASYNCCLK).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R329

(0149h)

Output_syst

em_clock

OPCLK_ENA

OPCLK Enable

0 = Disabled

1 = Enabled

7:3

OPCLK_DIV [4:0]

00h

OPCLK Divider

02h = Divide by 2

04h = Divide by 4

06h = Divide by 6

… (even numbers only)

1Eh = Divide by 30

Note that only even numbered divisions

(2, 4, 6, etc.) are valid selections.

All other codes are Reserved when the

OPCLK signal is enabled.

2:0

OPCLK_SEL [2:0]

000

OPCLK Source Frequency

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

All other codes are Reserved

The frequencies in brackets apply for

44.1kHz-related SYSCLK rates only (i.e.,

SAMPLE_RATE_n = 01XXX).

The OPCLK Source Frequency must be

less than or equal to the SYSCLK

frequency.

CS47L85 Datasheet(PDF) 253 Page - Cirrus Logic

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