CS47L85 datasheet(252/370 Pages) CIRRUS

252 / 370 page

CS47L85

252

Rev 4.3

FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT

GPn_FN = 010h, 011h, 012h.

Clock outputs derived from the FLLs may be output on a GPIO pin. The GPIO output from each FLLn (where ‘n’ is 1, 2 or 3)

is controlled by the respective FLLn_GPCLK_DIV and FLLn_GPCLK_ENA registers, as described in Table 97.

It is recommended to disable the clock output (FLLn_GPCLK_ENA=0) before making any change to the respective

FLLn_GPCLK_DIV register.

Note that the FLLn_GPCLK_DIV and FLLn_GPCLK_ENA registers affect the GPIO outputs only; they do not affect the FLL

frequency. The maximum output frequency supported for GPIO output is noted in the “Electrical Characteristics”.

The Frequency Locked Loop (FLL) Clock outputs may be output directly on a GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

See “Clocking and Sample Rates” for more details of the CS47L85 system clocking and for details of how to configure the

FLLs.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R394

(018Ah)

FLL1_GPIO

_Clock

7:1

FLL1_GPCLK_DI

V [6:0]

06h

FLL1 GPIO Clock Divider

00h to 05h = Reserved

06h= Divide by 6

07h = Divide by 7

08h = Divide by 8

09h = Divide by 9

…

7Fh = Divide by 127

(FGPIO = FVCO / FLL1_GPCLK_DIV)

FLL1_GPCLK_EN

FLL1 GPIO Clock Enable

0 = Disabled

1 = Enabled

R426

(01AAh)

FLL2_GPIO

_Clock

7:1

FLL2_GPCLK_DI

V [6:0]

06h

FLL2 GPIO Clock Divider

00h to 05h = Reserved

06h= Divide by 6

07h = Divide by 7

08h = Divide by 8

09h = Divide by 9

…

7Fh = Divide by 127

(FGPIO = FVCO / FLL2_GPCLK_DIV)

FLL2_GPCLK_EN

FLL2 GPIO Clock Enable

0 = Disabled

1 = Enabled

R458

(01CAh)

FLL3_GPIO

_Clock

7:1

FLL3_GPCLK_DI

V [6:0]

06h

FLL3 GPIO Clock Divider

00h to 05h = Reserved

06h= Divide by 6

07h = Divide by 7

08h = Divide by 8

09h = Divide by 9

…

7Fh = Divide by 127

(FGPIO = FVCO / FLL3_GPCLK_DIV)

FLL3_GPCLK_EN

FLL3 GPIO Clock Enable

0 = Disabled

1 = Enabled

Table 97 FLL Clock Output Control

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