CS47L85 datasheet(251/370 Pages) CIRRUS

251 / 370 page

CS47L85

Rev 4.3

251

BUTTON DETECT (GPIO INPUT)

GPn_FN = 001h.

Button detect functionality can be selected on a

GPIO pin by setting the respective GPIO registers as described in “GPIO

Control

”. The same functionality can be used to support a Jack Detect input function.

It is recommended to enable the GPIO input de-bounce feature when using GPIOs as button input or Jack Detect input.

The GPn_LVL fields may be read to determine the logic levels on a GPIO input, after the selectable de-bounce controls.

Note that GPn_LVL is not affected by the GPn_POL bit.

The de-bounced GPIO signals are also inputs to the Interrupt control circuit. An interrupt event is triggered on the rising and

falling edges of the GPIO input. The associated interrupt bits are latched once set; it can be polled at any time or used to

control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT)

GPn_FN = 001h.

The CS47L85 can be programmed to drive a logic high or logic low level on a

GPIO pin by selecting the “GPIO Output”

function as described in “GPIO Control”.

The output logic level is selected using the respective GPn_LVL bit. Note that the GPn

_LVL registers are ‘write only’ when

the respective GPIO pin is configured as an output.

The polarity of the GPIO output can be inverted using the GPn_POL registers. If GPn_POL=1, then the external output will

be the opposite logic level to GPn_LVL.

DSP GPIO (LOW LATENCY DSP INPUT/OUTPUT)

GPn_FN = 002h.

The DSP GPIO function provides an advanced I/O capability, supporting the requirements of the CS47L85 as a multi-

purpose sensor hub. The DSP GPIO pins are accessed using maskable sets of I/O control registers; this allows the selected

combinations of GPIOs to be controlled with ease, regardless of how the allocation of GPIO pins has been implemented in

hardware.

The DSP GPIO function is selected

by setting the respective GPIO registers as described in “GPIO Control”.

A full description of the DSP GPIO function is provided in the “DSP Peripheral Control” section.

The pin direction (input or output) is set according to the DSP GPIO configuration for each pin, whenever the respective

GPn_FN register is set to 002h. The GPn_DIR control bit has no effect in this case.

INTERRUPT (IRQ) STATUS OUTPUT

GPn_FN = 003h, 004h.

The CS47L85 has an Interrupt Controller which can be used to indicate when any selected Interrupt events occur. An

interrupt can be generated by any of the events described throughout the GPIO function definition above. Individual

interrupts may be masked in o

rder to configure the Interrupt as required. See “Interrupts” for further details.

The Interrupt Controller supports two separate Interrupt Request (IRQ) outputs. The IRQ1 or IRQ2 status may be output

directly on a

GPIO pin by setting the respective GPIO registers as described in “GPIO Control”.

Note that the IRQ1 status is output on the IRQ

¯¯¯ pin at all times.

CS47L85 Datasheet(PDF) 251 Page - Cirrus Logic

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