CS47L85 datasheet(247/370 Pages) CIRRUS

247 / 370 page

CS47L85

Rev 4.3

247

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6848

(1AC0h)

GPIO_Debou

nce_Config

3:0

GP_DBTIME

[3:0]

0000

GPIO Input de-bounce time

0h = 100us

1h = 1.5ms

2h = 3ms

3h = 6ms

4h = 12ms

5h = 24ms

6h = 48ms

7h = 96ms

8h = 192ms

9h = 384ms

Ah = 768ms

Bh to Fh = Reserved

Notes:

1. n is a number (1 to 40) that identifies the individual GPIO.

2. The default value of GPn_LVL depends upon whether the pin is actively driven by another

device. If the pin is actively driven, the bus-keeper will maintain this logic level. If the pin is not

actively driven, the bus-keeper may establish either a logic 1 or logic 0 as the initial input level.

Table 94 GPIO Control

GPIO FUNCTION SELECT

The available GPIO functions are described in Table 95.

The function of each GPIO is set using the GPn_FN register, where n identifies the GPIO pin (1 to 40). Note that the

respective GPn_DIR must also be set according to whether the function is an input or output.

GPn_FN

DESCRIPTION

COMMENTS

000h

Pin-specific alternate

function

Alternate functions supporting Digital Microphone,

Digital Audio Interface, Master Control Interface, and

PDM output functions.

001h

Button detect input / Logic

level output

GPn_DIR = 0: GPIO pin logic level is set by GPn_LVL.

GPn_DIR = 1: Button detect or logic level input.

002h

DSP GPIO

Low latency input/output for DSP functions.

003h

IRQ1 Output

Interrupt (IRQ1) output

0 = IRQ1 not asserted

1 = IRQ1 asserted

004h

IRQ2 Output

Interrupt (IRQ2) output

0 = IRQ2 not asserted

1 = IRQ2 asserted

010h

FLL1 Clock

Clock output from FLL1

011h

FLL2 Clock

Clock output from FLL2

012h

FLL3 Clock

Clock output from FLL3

018h

FLL1 Lock

Indicates FLL1 Lock status

0 = Not locked

1 = Locked

019h

FLL2 Lock

Indicates FLL2 Lock status

0 = Not locked

1 = Locked

01Ah

FLL3 Lock

Indicates FLL3 Lock status

0 = Not locked

1 = Locked

CS47L85 Datasheet(PDF) 247 Page - Cirrus Logic

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