CS47L85 datasheet(245/370 Pages) CIRRUS

245 / 370 page

CS47L85

Rev 4.3

245

GENERAL PURPOSE INPUT / OUTPUT

The CS47L85 provides a number of GPIO functions to enable interfacing and detection of external hardware and to provide

logic outputs to other devices. The GPIO input functions can be used to generate an Interrupt (IRQ) event. The GPIO and

Interrupt circuits support the following functions:



Pin-specific alternative functions for external interfaces (AIF, DMIC, PDM, MIF)



Logic input / Button detect (GPIO input)



Logic ‘1’ and logic ‘0’ output (GPIO output)



Interrupt (IRQ) status output



Clock output



Frequency Locked Loop (FLL) status output



Frequency Locked Loop (FLL) Clock output



IEC-60958-3 compatible S/PDIF output



Pulse Width Modulation (PWM) Signal output



Asynchronous Sample Rate Converter (ASRC) Lock status



Over-Temperature, Speaker Short Circuit Protection, and Speaker Shutdown status output



General Purpose Timer status output



Event Logger FIFO buffer status output

Note that the GPIO pins are referenced to different power domains (DBVDD1, DBVDD2, DBVDD3 or DBVDD4), as noted

in the “Pin Description” section.

Logic input and output (GPIO) can be supported in two different ways on the CS47L85

. The ‘standard’ mechanism described

in this section provides a comprehensive suite of options including input de-bounce, and selectable output drive configuration.

The ‘DSP GPIO’ circuit is tailored towards more advanced requirements typically demanded by DSP software features. The

DSP GPIO functions are described in the

“DSP Peripheral Control” section.

The CS47L85 also incorporates a General Purpose Switch feature, which can be used as a controllable analogue switch;

details of this are provided at the end of this “General Purpose Input / Output” section.

GPIO CONTROL

For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO pin (1 to 40). The pin

direction, set by GPn_DIR, must be set according to function selected by GPn_FN.

When a pin is configured as a GPIO input (GPn_DIR = 1, GPn_FN = 001h), the logic level at the pin can be read from the

respective GPn_LVL bit. Note that GPn_LVL is not affected by the GPn_POL bit.

A de-bounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin by setting

the respective GPn_DB bit. The de-bounce circuit uses the 32kHz clock, which must be enabled whenever input de-bounce

functions are required. The de-bounce time is configurable using the GP_DBTIME register.

See “Clocking and Sample Rates”

for further details of the CS47L85 clocking configuration.

Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt event. An interrupt

event is triggered on the rising and falling edges of the GPIO input. The associated interrupt bit is latched once set; it can

polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

Integrated pull-up and pull-down resistors are provided on each of the GPIO pins; these can be configured independently

using the GPn_PU and GPn_PD fields. When the pull-up and pull-down control bits are both enabled, the CS47L85 provides

a ‘bus keeper’ function on the respective pin. The bus keeper function holds the logic level unchanged whenever the pin is

undriven (e.g., if the signal is tri-stated).

Note that the bus keeper is enabled by default on all GPIO pins and, if not actively driven, may result in either a logic 0 or

logic 1 at the respective input on start-up. If an external pull resistor is connected (e.g., to control the logic level in Sleep

Mode), the chosen resistance should take account of the bus keeper resistance (see “Electrical Characteristics”). A ‘strong’

pull resistor (e.g., 10k

Ω) is required, if a specific start-up condition is to be forced by the external pull component.

When a pin is configured as a GPIO output (GPn_DIR = 0, GPn_FN = 001h), its level can be set to logic 0 or logic 1 using

the GPn_LVL field. Note that the GPn

_LVL registers are ‘write only’ when the respective GPIO pin is configured as an output.

When a pin is configured as an output (GPn_DIR = 0), the polarity can be inverted using the GPn_POL bit. When GPn_POL

= 1, then the selected output function is inverted. In the case of Logic Level output (GPn_FN = 001h), the external output

CS47L85 Datasheet(PDF) 245 Page - Cirrus Logic

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