CS47L85 datasheet(246/370 Pages) CIRRUS

246 / 370 page

CS47L85

246

Rev 4.3

will be the opposite logic level to GPn_LVL when GPn_POL = 1. Note that, if GPn_FN=000h or 002h, then the GPn_POL

bit has no effect on the respective GPIO pin.

A GPIO output can be either CMOS driven or Open Drain. This is selected on each pin using the respective GPn_OP_CFG

bit. Note that, if GPn_FN=000h or 002h, then the GPn_OP_CFG bit has no effect on the respective GPIO pin; see Pin

Description

” for the output configuration in this case.

The register fields that control the GPIO pins are described in Table 94.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5888

(1700h)

GPIO1_CTRL

R5966

(174Eh)

GPIO40_CTR

L_1

GPn_LVL

see notes

GPIOn level. Write to this bit to set

a GPIO output. Read from this bit to

read GPIO input level.

For output functions only, when

GPn_POL is set, the register is the

opposite logic level to the external

pin.

Note that the GPn_LVL register is

‘write only’ when GPn_DIR=0.

GPn_OP_CFG

GPIOn Output Configuration

0 = CMOS

1 = Open Drain

Note that, if GPn_FN=000h or 002h,

then this bit has no effect on the

GPIOn output.

GPn_DB

GPIOn Input De-bounce

0 = Disabled

1 = Enabled

GPn_POL

GPIOn Output Polarity Select

0 = Non-inverted (Active High)

1 = Inverted (Active Low)

Note that, if GPn_FN=000h or 002h,

then this bit has no effect on the

GPIOn output.

8:0

GPn_FN [8:0]

001h

GPIOn Pin Function

(see Table 95 for details)

R5889

(1701h)

GPIO1_CTRL

R5967

(174Fh)

GPIO40_CTR

L_2

GPn_DIR

GPIOn Pin Direction

0 = Output

1 = Input

The GPn_DIR bit has no effect if

GPn_FN=000h or 002h

If GPn_FN=000h, then the pin

direction is selected by the

applicable pin-specific function.

If GPn_FN=002h, then the pin

direction is set according to the

DSP GPIO configuration.

GPn_PU

GPIOn Pull-Up Enable

0 = Disabled

1 = Enabled

Note - when GPn_PD and GPn_PU

are both set to ‘1’, then a ‘bus

keeper’ function is enabled on the

respective GPIOn pin.

GPn_PD

GPIOn Pull-Down Enable

0 = Disabled

1 = Enabled

Note - when GPn_PD and GPn_PU

are both set to ‘1’, then a ‘bus

keeper’ function is enabled on the

respective GPIOn pin.

CS47L85 Datasheet(PDF) 246 Page - Cirrus Logic

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