CS47L85 datasheet(244/370 Pages) CIRRUS

244 / 370 page

CS47L85

244

Rev 4.3

The ‘Always-On’ digital input / output pins are listed in Table 93. All other digital input pins have no effect in Sleep mode; all

other digital output pins are undriven (floating).

The IRQ

¯¯¯ output is normally de-asserted in Sleep mode. Note that, in Sleep mode, the IRQ

¯¯¯ output can only be asserted in

response to the JACKDET1 or JACKDET2 inputs, as described below. If the IRQ

¯¯¯ output is asserted in Sleep mode, it can

only be de-asserted after a Wake-Up transition.

Output drivers and bus keepers are disabled in Sleep Mode, for all pins not on the always-on domain; this means that the

logic level on these pins is undefined. If a defined logic level is required during Sleep Mode (e.g., as input to another device),

an external pull resistor may be required. If an external pull resistor is connected to a pin that also supports a bus keeper

function, the pull resistance should be chosen carefully, taking into account the resistance of the

bus keeper. See “General

Purpose Input / Output

” for specific notes concerning the GPIO pins.

PIN NAME

DESCRIPTION

REFERENCE

IRQ

¯¯¯

Interrupt Request (IRQ) output

See “Interrupts”

JACKDET1

Jack Detect input 1

See “External Accessory Detection”

JACKDET2

Jack Detect input 2

See “External Accessory Detection”

LDOENA

Enable pin for LDO1

See “Charge Pumps, Regulators and

Voltage Reference

”

RESET

¯¯¯¯¯¯

Digital Reset input (active low)

See “Hardware Reset, Software Reset,

Wake-Up, and Device ID

”

Table 93

Sleep Mode ‘Always-On’ Digital Input Pins

The ‘Always-On’ functionality includes the JD1 and JD2 control signals, which provide support for the low-power Sleep mode.

The MICDET Clamp status signal is also supported; this is controlled by a selectable logic function, derived from JD1 and/or

JD2.

The JD1, JD2 and MICDET Clamp status signals are derived from the JACKDET1 and JACKDET2 inputs, and can be used

to trigger the Interrupt Controller.

The Interrupt (IRQ

¯¯¯

) functionality associated with these signals is part of the ‘Always-On’ functionality, enabling the CS47L85

to provide indication of jack insertion or jack removal to the host processor in Sleep mode.

See “Interrupts” for further details.

Note that the JACKDET1 and JACKDET2 inputs will not result in a Wake-Up transition directly; a Wake-Up transition will

only occur by re-application of DCVDD. In a typical application, the JACKDETn inputs will provide a signal to the Applications

Processor, via the IRQ

¯¯¯ output; if a Wake-Up transition is required, this is triggered by the Applications Processor asserting

the LDOENA pin.

The JD1 and JD2 sign

als are derived from the Jack Detect function (see “External Accessory Detection”). These inputs can

be used to trigger a response to a jack insertion or jack removal detection.

When these signals are enabled, the JD1 and JD2 signals indicate the status of the JACKDET1 and JACKDET2 input pins

respectively. See Table 85 for details of the associated control registers.

The MICDET Clamp status is controlled by the JD1 and/or JD2 signals (see “External Accessory Detection”). The

configurable logic provides flexibility in selecting the appropriate conditions for activating the MICDET Clamp. The clamp

status can be used to trigger a response to a jack insertion or jack removal detection.

The MICDET Clamp function is configured using the MICD_CLAMP_MODE register, as described in Table 86.

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