CS47L85 datasheet(243/370 Pages) CIRRUS

243 / 370 page

CS47L85

Rev 4.3

243

LOW POWER SLEEP CONFIGURATION

The CS47L85 supports a low-

power ‘Sleep’ mode, where most functions are disabled, and power consumption is minimised.

The CS47L85 enters Sleep mode when the DCVDD supply is removed. In a typical application, this is controlled via the

LDOENA pin, which enables/disables the LDO1 regulator, thus enabling/disabling the DCVDD supply.

Whilst in the Sleep mode, the CS47L85 can generate an Interrupt Event in response to a change in voltage on the

JACKDET1 or JACKDET2 pins. This enables a jack insertion event (or other digital logic transition) to be used to trigger a

Wake-Up of the CS47L85.

Note that the AVDD, DBVDD1 supplies must be present throughout the Sleep mode duration. When LDO1 is used to provide

the DCVDD supply, then LDOVDD must also be present in Sleep mode.

The system clocks (SYSCLK, ASYNCCLK, DSPCLK) should each be disabled before selecting Sleep mode. The external

clock input (MCLKn) may also be stopped, if desired.

Access to the CS47L85 register map using any of the Control Interfaces should be ceased before selecting Sleep mode.

Sel

ected functions and control registers are maintained via an ‘Always-On’ internal supply domain in Sleep mode. The

‘Always-On’ control registers are listed in Table 92. These registers are maintained (i.e., not reset) in Sleep mode.

Note that the Control Interface is not supported in Sleep mode. Read/Write access to the ‘Always-On’ registers is not possible

in Sleep mode.

ADDRESS

LABEL

REFERENCE

R710 (02C6h)

MICD_CLAMP_OVD

See “External Accessory Detection”

MICD_CLAMP_MODE [3:0]

R723 (02D3h)

JD2_ENA

JD1_ENA

R6150 (1806h)

MICD_CLAMP_FALL_EINT1

See

“Interrupts”

MICD_CLAMP_RISE_EINT1

JD2_FALL_EINT1

JD2_RISE_EINT1

JD1_FALL_EINT1

JD1_RISE_EINT1

R6214 (1846h)

IM_MICD_CLAMP_FALL_EINT1

IM_MICD_CLAMP_RISE_EINT1

IM_JD2_FALL_EINT1

IM_JD2_RISE_EINT1

IM_JD1_FALL_EINT1

IM_JD1_RISE_EINT1

R6784 (1A80h)

IM_IRQ1

IRQ_POL

IRQ_OP_CFG

R6864 (1AD0h)

RESET_PU

See “Hardware Reset, Software

Reset, Wake-Up, and Device ID

”

RESET_PD

Table 92

Sleep Mode ‘Always-On’ Control Registers

CS47L85 Datasheet(PDF) 243 Page - Cirrus Logic

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