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CS47L85 Datasheet(PDF) 254 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 254 Page - Cirrus Logic

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CS47L85
254
Rev 4.3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R330
(014Ah)
Output_asy
nc _lock
15
OPCLK_ASYNC_
ENA
0
OPCLK_ASYNC Enable
0 = Disabled
1 = Enabled
7:3
OPCLK_ASYNC_
DIV [4:0]
00h
OPCLK_ASYNC Divider
02h = Divide by 2
04h = Divide by 4
06h = Divide by 6
… (even numbers only)
1Eh = Divide by 30
Note that only even numbered divisions
(2, 4, 6, etc.) are valid selections.
All other codes are Reserved when the
OPCLK_ASYNC signal is enabled.
2:0
OPCLK_ASYNC_
SEL [2:0]
000
OPCLK_ASYNC Source Frequency
000 = 6.144MHz (5.6448MHz)
001 = 12.288MHz (11.2896MHz)
010 = 24.576MHz (22.5792MHz)
011 = 49.152MHz (45.1584MHz)
All other codes are Reserved
The frequencies in brackets apply for
44.1kHz-related ASYNCCLK rates only
(i.e., ASYNC_SAMPLE_RATE_n =
01XXX).
The OPCLK_ASYNC Source Frequency
must be less than or equal to the
ASYNCCLK frequency.
Table 98 OPCLK and OPCLK_ASYNC Control
PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT
GPn_FN = 048h, 049h.
The CS47L85 incorporates two Pulse Width Modulation (PWM) signal generators which can be enabled as GPIO outputs.
The duty cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control
register setting.
The Pulse Width Modulation (PWM) outputs may be output directly on a GPIO pin by setting the respective GPIO registers
as described in “GPIO Control”.
See “Digital Core” for details of how to configure the PWM signal generators.
SPDIF AUDIO OUTPUT
GPn_FN = 04Ch.
The CS47L85 incorporates an IEC-60958-3 compatible S/PDIF transmitter, which can be selected as a GPIO output. The
S/PDIF transmitter supports stereo audio channels, and allows full control over the S/PDIF validity bits and channel status
information.
The S/PDIF signal may be output directly on a
GPIO pin by setting the respective GPIO registers as described in “GPIO
Control
”.
See “Digital Core” for details of how to configure the S/PDIF output generator.



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