The peak-to-peak inductor ripple current is calculated by Equation 4.

IN

L P P

SW

V

D

I

L

f

u

'

u

(4)

where

• L is the inductance value of the inductor

• fSW is the switching frequency

• D is the duty cycle

• VIN is the input voltage of the boost converter

8.3.5 Pass-Through Operation

When the input voltage is higher than the setting output voltage, the output voltage is higher than the target

regulation voltage, the device works in pass-through mode. When the output voltage is 101% of the setting

target voltage, the TPS61033 stops switching and fully turns on the high-side PMOS FET. The output voltage

is the input voltage minus the voltage drop across the DCR of the inductor and the RDS(on) of the PMOS FET.

When the output voltage drops below the 97% of the setting target voltage as the input voltage declines or the

load current increases, the TPS61033 resumes switching again to regulate the output voltage.

8.3.6 Power Good Indicator

The TPS61033 integrates a power good indicator to simplify sequencing and supervision. The power-good

output consists of an open-drain NMOS, requiring an external pullup resistor connect to a suitable voltage

supply. The PG pin goes high with a typical 1.3 ms delay time after VOUT is between 93% (typical) and 107%

(typical) of the target output voltage. When the output voltage is out of the target output voltage window, the PG

pin immediately goes low with a 33 μs deglitch filter delay. This deglitch filter also prevents any false pulldown of

the PGOOD due to transients. When EN is pulled low, the PG pin is also forced low with a 33 μs deglitch filter

delay. If not used, the PG pin can be left floating or connected to GND.

8.3.7 Implement Output Discharge by PG function

The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage and to

let the output voltage close to 0 V quickly when the device is being disabled. TPS61033 can implement output

discharge function by PG function that requires a RDummy resistor connected between PG pin and Vout pin. PG

is an open drain NMOS architecture with up to 50 mA current capability, the PG pin will become logic high when

the output voltage reaches the target value, so the dummy load resistor will not lead any power loss during

normal operation. When the EN pin gets low, the TPS61033 will be disabled and meanwhile the PG pin will get

low with a typical 33μs glitch time (tglitch). With PG pin keep low, the RDummy will working as a dummy load to

discharge output voltage. Changing RDummy can adjust the output discharge rate.

Output

Voltage

time

PG

time

tglitch

Output voltage

discharge from RDummy

EN

VIN

EN

SW

VOUT

FB

GND

L1

C1

C2

MODE

PG

R1

R2

RDummy

Figure 8-1. Implement Output Discharge by PG function

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TPS61033

SLVSGI6 – OCTOBER 2022

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