Vout (5V o set)

100mV/div

Output Current

500mA/div

Time Scale: 500us/div

VIN = 3.3 V, VOUT = 5 V, IOUT = 50 mA to 2 A Sweep

Figure 9-8. Load Sweep

Vin

2V/div

Vout (5V o set)

100mV/div

Time Scale: 5ms/div

Inductor Current

2A/div

VIN = 1 V to 4.5 V Sweep, VOUT = 5 V, IOUT = 1 A

Figure 9-9. Line Sweep

Vout

2V/div

SW

2V/div

Time Scale: 2 s/div

Inductor Current

2A/div

VIN = 3.3 V, VOUT = 5 V, IOUT = 2 A

Figure 9-10. Output Short Protection (Entry)

Vout

2V/div

SW

2V/div

Time Scale: 100 s/div

Inductor Current

2A/div

VIN = 3.3 V, VOUT = 5 V, IOUT = 2 A

Figure 9-11. Output Short Protection (Recover)

9.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 1.8 V to 5.5 V. This input supply

must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk

capacitance may be required in addition to the ceramic bypass capacitors. A typical choice is a tantalum or

aluminum electrolytic capacitor with a value of 100 µF. Output current of the input power supply must be rated

according to the supply voltage, output voltage, and output current of the TPS61033.

9.4 Layout

9.4.1 Layout Guidelines

As for all switching power supplies, especially those running at high switching frequency and high currents,

layout is an important design step. If the layout is not carefully done, the regulator could suffer from instability

and noise problems. To maximize efficiency, switch rise and fall time are very fast. To prevent radiation of high

frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize

the length and area of all traces connected to the SW pin, and always use a ground plane under the switching

regulator to minimize interplane coupling. The input capacitor needs not only to be close to the VIN pin, but also

to the GND pin in order to reduce input supply ripple.

The most critical current path for all boost converters is from the switching FET, through the rectifier FET, then

the output capacitors, and back to ground of the switching FET. This high current path contains nanosecond rise

and fall time and must be kept as short as possible. Therefore, the output capacitor not only must be close to the

VOUT pin, but also to the GND pin to reduce the overshoot at the SW pin and VOUT pin.

For better thermal performance, TI suggest to make copper polygon connected with each pin bigger.

TPS61033

SLVSGI6 – OCTOBER 2022

www.ti.com

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