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AM625 Datasheet(PDF) 134 Page - Texas Instruments

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Part # AM625
Description  AM62x Sitara™ Processors
PDF  255 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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AM625 Datasheet(HTML) 134 Page - Texas Instruments

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Table 7-38. CPTS Switching Characteristics
see Figure 7-33
NO.
PARAMETER
DESCRIPTION
SOURCE
MIN
MAX
UNIT
T6
tw(TS_COMPH)
Pulse duration, TS_COMP high
36P(1) - 2
ns
T7
tw(TS_COMPL)
Pulse duration, TS_COMP low
36P(1) - 2
ns
T8
tw(TS_SYNCH)
Pulse duration, TS_SYNC high
36P(1) - 2
ns
T9
tw(TS_SYNCL)
Pulse duration, TS_SYNC low
36P(1) - 2
ns
T10
tw(SYNC_OUTH)
Pulse duration, SYNCn_OUT high
TS_SYNC
36P(1) - 2
ns
GENF
5P(1) - 2
ns
T11
tw(SYNC_OUTL)
Pulse duration, SYNCn_OUT low
TS_SYNC
36P(1) - 2
ns
GENF
5P(1) - 2
ns
(1)
P = functional clock period in ns.
TS_COMP
T6
T7
TS_SYNC
T8
T9
SYNCn_OUT
T10
T11
Figure 7-33. CPTS Switching Characteristics
For more information, see Data Movement Architecture (DMA) chapter in the device TRM.
7.11.5.3 CSI-2
Note
For more information, see the Camera Streaming Interface Receiver (CSI_RX_IF) section in the
device TRM.
The CSI_RX_IF deals with the processing of the pixel data coming from an external image sensor. It is a key
component for the following multimedia applications: camera viewfinder, video record, and still image capture.
The CSI_RX_IF has a primary serial interface CSI-2 port (CSIRX0) compliant with the MIPI D-PHY RX
specification v1.2 and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock
lane in synchronous mode, double data rate. Refer to the MIPI specifications for timing details.
• Support for 1,2,3 or 4 data lane mode up to 1.5Gbps
AM625, AM623
SPRSP58A – JUNE 2022 – REVISED NOVEMBER 2022
www.ti.com
134
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Product Folder Links: AM625 AM623



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