AM625 datasheet(137/255 Pages) TI

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Table 7-42. DSS Switching Characteristics

see Figure 7-36

NO.

PARAMETER

MIN

MAX

UNIT

tc(pclk)

Cycle time, VOUT(x)_PCLK(2)

6.06

tw(pclkL)

Pulse duration, VOUT(x)_PCLK(2) low

0.475P(1)

tw(pclkH)

Pulse duration, VOUT(x)_PCLK(2) high

0.475P(1)

td(pclkV-dataV)

Delay time, VOUT(x)_PCLK(2) transition to VOUT(x)_DATA[23:0](2)

transition

-0.68

1.78

td(pclkV-ctrlL)

Delay time, VOUT(x)_PCLK(2) transition to control signals

VOUT(x)_VSYNC(2), VOUT(x)_HSYNC(2), VOUT(x)_DE(2) falling

edge

-0.68

1.78

(1)

P = VOUT(x)_PCLK cycle time in ns

(2)

x in VOUT(x) = 0

VOUT(x)_PCLK

VOUT(x)_VSYNC

VOUT(x)_HSYNC

VOUT(x)_DATA[23:0]

VOUT(x)_DE

data_1 data_2

data_n

DPI_TIMING_01

VOUT

_PCLK

(x)

Falling-edge Clock Reference

Rising-edge Clock Reference

The assertion of data can be programmed to occur on the falling or rising edge of the pixel clock. Refer to Display Subsystem (DSS)

section in Peripherals chapter in the device TRM.

The polarity and pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS) section

in Peripherals chapter in the device TRM.

The VOUT(x)_PCLK frequency is configurable, refer to Display Subsystem section in Peripherals chapter in the device TRM.

Figure 7-36. DSS Switching Characteristics

For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter of the

device TRM.

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AM625, AM623

SPRSP58A – JUNE 2022 – REVISED NOVEMBER 2022

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